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Difference between revisions of "intel/xeon d/d-1557"
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|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core)
 
|l2 extra=(per core)
|l3 cache=18 MB
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|l3 cache=18 MiB
|l3 break=8x1.5 MB
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|l3 break=8x1.5 MiB
|l3 desc=
 
 
|l3 extra=(per core)
 
|l3 extra=(per core)
 
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Revision as of 02:04, 19 September 2016

Template:mpu The Xeon D-1557 is a 64-bit dodeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1557 operates at 1.5 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 384 KB
"KB" is not declared as a valid unit of measurement for this property.
12x32 KB 8-way set associative (per core)
L1D$ 384 KB
"KB" is not declared as a valid unit of measurement for this property.
12x32 KB 8-way set associative (per core)
L2$ 3 MB
"MB" is not declared as a valid unit of measurement for this property.
12x256 KB 8-way set associative (per core)
L3$ 18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
8x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface Yes
KR4 interface No
KX interface Yes
KX4 interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

Facts about "Xeon D-1557 - Intel"
l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description8-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +