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Difference between revisions of "intel/xeon d/d-1557"
< intel‎ | xeon d

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| socket type        = BGA
 
| socket type        = BGA
 
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The '''{{intel|Xeon D}}-1557''' is a {{arch|64}} dodeca-core [[x86-64]] microserver SoC that was introduced by [[Intel]] in February of 2016. The D-1557 operates at 1.5 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the [[intel/microarchitectures/broadwell|Broadwell]] [[microarchitecture]] and manufactured in [[14 nm process]], has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).
  
 
== Cache ==
 
== Cache ==
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|l2 extra=(per core)
 
|l2 extra=(per core)
 
|l3 cache=18 MB
 
|l3 cache=18 MB
 +
|l3 break=8x1.5 MB
 
|l3 desc=
 
|l3 desc=
−
|l3 extra=(shared)
+
|l3 extra=(per core)
 +
}}
 +
 
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR3L-1333
 +
| type 2            = DDR3L-1600
 +
| type 3            = DDR4-1600
 +
| type 4            = DDR4-1867
 +
| type 5            = DDR4-2133
 +
| controllers        = 1
 +
| channels          = 2
 +
| ecc support        = Yes
 +
| max bandwidth      =
 +
| bandwidth schan    =
 +
| bandwidth dchan    =
 +
| max memory        = 128 GB
 +
}}
 +
 
 +
== Expansions ==
 +
{{mpu expansions
 +
| pcie revision      = 2.0
 +
| pcie revision 2    = 3.0
 +
| pcie lanes        = 8
 +
| pcie lanes 2      = 32
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
| usb revision      = 2.0
 +
| usb revision 2    = 3.0
 +
| usb ports          = 8
 +
| sata ports        = 6
 +
| integrated lan    = Yes
 +
| uart              = Yes
 +
}}
 +
 
 +
== Networking ==
 +
{{soc networking
 +
| SFI interface    = Yes
 +
| KR interface      = No
 +
| KR4 Interface    = No
 +
| KX Interface      = Yes
 +
| KX4 Interface    = No
 +
| 10Base-T          = No
 +
| 100Base-T        = No
 +
| 1000Base-T        = Yes
 +
| 10GBase-T        = Yes
 +
}}
 +
 
 +
== Features ==
 +
{{mpu features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| ht          = Yes
 +
| tbt2        = Yes
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4        = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 
}}
 
}}

Revision as of 01:29, 12 April 2016

Template:mpu The Xeon D-1557 is a 64-bit dodeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1557 operates at 1.5 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell's Cache
Cache Info [Edit Values]
L1I$ 384 KB
"KB" is not declared as a valid unit of measurement for this property.
 		12x32 KB 8-way set associative (per core)
L1D$ 384 KB
"KB" is not declared as a valid unit of measurement for this property.
 		12x32 KB 8-way set associative (per core)
L2$ 3 MB
"MB" is not declared as a valid unit of measurement for this property.
 		12x256 KB 8-way set associative (per core)
L3$ 18 MB
"MB" is not declared as a valid unit of measurement for this property.
 		8x1.5 MB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

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l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description8-way set associative +