Editing intel/xeon bronze

{{intel title|Xeon Bronze}}
{{ic family
| title             = Xeon Bronze
| image             = xeon bronze (2017).png
| caption           = Xeon Bronze Logo
| developer         = Intel
| manufacturer      = Intel
| type              = Microprocessors
| first announced   = May 4, 2017
| first launched    = July 11, 2017
| arch              = x86 server multiprocessors
| isa               = x86-64
| microarch         = Skylake
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 
| clock max         = 
| package           = FCLGA-3647
| socket            = LGA-3647

| succession         = Yes
| predecessor        = Xeon E7
| predecessor link   = intel/xeon e7
| predecessor 2      = Xeon E5
| predecessor 2 link = intel/xeon e5
| successor          = 
| successor link     = 
}}
'''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server-class microprocessors introduced by [[Intel]] in 2017.

== Overview ==
Released in July 2017, the Xeon Bronze are the successor to the {{intel|Xeon E5}}/{{intel|Xeon E7|E7}} families. Xeon Bronze is geared toward entry-level dual-socket server and workstation microprocessors. Those processors are ideally positioned for price-sensitive applications which require light-range workloads with enhanced security features and large memory. Additionally, those processors incorporate a number of {{intel|Ultra Path Interconnect}} (UPI) links. Unlike the higher tier Xeon families, the Xeon Bronze doesn't have {{intel|Turbo Boost Technology}} or {{intel|Hyper-Threading}} support.

== Members ==
=== 3100-Series (Skylake) ===
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
First-generation Xeon Bronze was introduced in July 2017. Those processors were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which moved to a tile architecture, introduced the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy. All of the bronze 3100-series microprocessors feature dual-socket capabilities with up to [[8 cores]] and 8 threads. Additionally, all Xeon Bronze processors support:

* '''TDP:''' 85 W
* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory.
* '''I/O:''' 48 PCIe 3 lanes
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).

All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5">
{{comp table header|main|8:List of Skylake-based Xeon Bronze Processors}}
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |format=template
 |template=proc table 3
 |userparam=10
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]}}
</table>
{{comp table end}}

=== 3200-Series (Cascade Lake) ===
{{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
Second-generation Xeon Scalable Bronze was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 3200-series Xeon Bronze processors support:

* '''TDP:''' 85 W
* '''Mem:''' 1 TiB hexa-channel DDR4-2133 ECC memory.
* '''I/O:''' 48 PCIe 3 lanes
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).

All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5">
{{comp table header|main|8:List of Cascade Lake-based Xeon Bronze Processors}}
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Cascade Lake]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |valuesep=,
 |format=template
 |template=proc table 3
 |userparam=10
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Cascade Lake]]}}
</table>
{{comp table end}}

== See also ==
* {{\\|Xeon Silver}}
* {{\\|Xeon Gold}}
* {{\\|Xeon Platinum}}
designer	Intel +
first announced	May 4, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon bronze +
instance of	microprocessor family +
instruction set architecture	x86-64 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	Skylake +
name	Xeon Bronze +
package	FCLGA-3647 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-3647 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +