From WikiChip
Difference between revisions of "intel/process-architecture-optimization"
< intel

Line 1: Line 1:
{{intel title|Process-Architecture-Optimization (PAO)}}
+
{{intel title|P2 (PAO)}}
 
'''[[name::Process-Architecture-Optimization]]''' is a [[instance of::development model]] introduced by [[Intel]] for their mainstream microprocessors in [[2016]] following the phase-out of their {{intel|Tick-Tock}} model. The change is a result of the increase in cost and complexity of advancing lithography processes in the past decade. Under the new model the amount of time utilized for any given process technology is lengthen.
 
'''[[name::Process-Architecture-Optimization]]''' is a [[instance of::development model]] introduced by [[Intel]] for their mainstream microprocessors in [[2016]] following the phase-out of their {{intel|Tick-Tock}} model. The change is a result of the increase in cost and complexity of advancing lithography processes in the past decade. Under the new model the amount of time utilized for any given process technology is lengthen.
 +
 +
Under the Process-Architecture-Optimization Model:
 +
 +
* '''Process''' -  With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yielded better performance and energy saving. During a tick, usually just a few features and improvements and new instructions are introduced.
 +
 +
* '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities.
 +
 +
* '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures.

Revision as of 03:34, 3 August 2016

Process-Architecture-Optimization is a development model introduced by Intel for their mainstream microprocessors in 2016 following the phase-out of their Tick-Tock model. The change is a result of the increase in cost and complexity of advancing lithography processes in the past decade. Under the new model the amount of time utilized for any given process technology is lengthen.

Under the Process-Architecture-Optimization Model:

  • Process - With each process, Intel advances their manufacturing process technology in line with Moore's Law. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their previous microarchitecture to the new process which inherently yielded better performance and energy saving. During a tick, usually just a few features and improvements and new instructions are introduced.
  • Architecture - With each architecture, Intel uses the their latest manufacturing process technology from their "process" to manufacture a newly designed microarchitecture. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities.
  • Optimization - With each optimization, Intel improves upon their previous microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures.
instance ofdevelopment model +
nameProcess-Architecture-Optimization +