Editing intel/process-architecture-optimization

{{intel title|Process-Architecture-Optimization (PAO)}}
'''[[name::Process-Architecture-Optimization]]''' is a [[instance of::development model]] introduced by [[Intel]] for their mainstream microprocessors in [[2016]] following the phase-out of their {{intel|Tick-Tock}} model as a result of major delays and challenges involving their [[10 nm process]].

Under the Process-Architecture-Optimization Model:

* '''Process''' -  With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yields better performance and energy saving. During a "process", usually just a few features and improvements are introduced.

* '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New [[instruction set|instructions]] are often added during this cycle stage.

* '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additionally the process itself enjoys various refinements as it matures. (For example with {{intel|Kaby Lake|l=arch}}, an optimized process called "14 nm+" is used. The enhanced process had a number of transistor-level modifications done to it (e.g. taller fins) allowing for higher frequency at identical voltage levels.)

== Roadmap ==
[[File:pao.png|right|500px]]
{| class="wikitable"
! colspan="4" style="background:#D6D6FF;" | Intel PAO Roadmap
|-
!Cycle !! [[technology node|Process]] !! Introduction !! Microarchitecture
|-
| Process || [[14 nm]] || 2014 || {{intel|Broadwell|l=arch}}
|-
| Architecture || [[14 nm]] || 2015 || {{intel|Skylake (Client)|l=arch}}
|-
| Optimization || [[14 nm|14 nm+]] || 2016 || {{intel|Kaby Lake|l=arch}}
|-
| Optimization || [[14 nm|14 nm++]] || 2017 || {{intel|Coffee Lake|l=arch}}, {{intel|Skylake (Server)|l=arch}}
|-
| Optimization || [[14 nm|14 nm++]] || 2018 || {{intel|Amber Lake|l=arch}} {{intel|Whiskey Lake|l=arch}}
|-
| Optimization || [[14 nm|14 nm++]] || 2019 || {{intel|Cascade Lake|l=arch}}
|-
| Optimization || [[14 nm|14 nm++]] || 2020 || {{intel|Cooper Lake|l=arch}}, {{intel|Comet Lake|l=arch}}
|-
| Optimization || [[14 nm|14 nm++]] || 2021 || {{intel|Rocket Lake|l=arch}}
|}

[[Category:intel]]
instance of	development model +
name	Process-Architecture-Optimization +