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{{intel title|Process Technology}}
 
{{intel title|Process Technology}}
This article details [[Intel]]'s [[Semiconductor Process Technology]].
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This article details details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.
  
 
== Timeline ==
 
== Timeline ==
Line 14: Line 14:
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22= 1120 µm²
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22= 1120 µm²
 
   |a3=L<sub>g</sub>  |d3=3.0 µm
 
   |a3=L<sub>g</sub>  |d3=3.0 µm
   |a4=CPP            |d4=7 µm   |a42=MMP            |d42=11 µm
+
   |a4=CPP            |d4=7 µm     |a42=MMP            |d42=11 µm
 
}}
 
}}
 
{{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm
 
{{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm
 
   |archs=
 
   |archs=
 
   |a1=T<sub>ox</sub> |d1=40 nm    |a12=Gate Dielectric |d12=
 
   |a1=T<sub>ox</sub> |d1=40 nm    |a12=Gate Dielectric |d12=
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM (HD)      |d22=1740 µm²
+
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM           |d22=1740 µm²
 
   |a3=L<sub>g</sub>  |d3=2.0 µm
 
   |a3=L<sub>g</sub>  |d3=2.0 µm
 
   |a4=CPP            |d4=5.6 µm    |a42=MMP            |d42=8 µm
 
   |a4=CPP            |d4=5.6 µm    |a42=MMP            |d42=8 µm
 
}}
 
}}
{{intel proc tech |year=1982 |name=P646 (CHMOS III) |mlayers=1 |node=1.5 µm
+
{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm
 
   |archs=80286, 80386
 
   |archs=80286, 80386
 
   |a1=T<sub>ox</sub> |d1=25 nm    |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O
 
   |a1=T<sub>ox</sub> |d1=25 nm    |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM (HD)      |d22=951.7 µm²
+
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM           |d22=951.7 µm²
 
   |a3=L<sub>g</sub>  |d3=1.5 µm
 
   |a3=L<sub>g</sub>  |d3=1.5 µm
 
   |a4=CPP            |d4=4.0 µm    |a42=MMP            |d42=6.4 µm
 
   |a4=CPP            |d4=4.0 µm    |a42=MMP            |d42=6.4 µm
Line 62: Line 62:
 
{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
 
{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
 
   |archs=NetBurst
 
   |archs=NetBurst
   |a1=L<sub>g</sub>  |d1=130 nm
+
   |a1=T<sub>ox</sub> |d1=2.0 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=T<sub>ox</sub> |d2=2.0 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+
   |a2=V<sub>dd</sub> |d2=1.6 V     |a22=SRAM            |d22=5.59 µm²
   |a3=V<sub>dd</sub> |d3=1.6 V
+
  |a3=L<sub>g</sub>  |d3=130 nm
 +
  |a4=CPP            |d4=480 nm    |a42=MMP            |d42=500 nm
 
}}
 
}}
 
{{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
 
{{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
 
   |archs=Pentium M
 
   |archs=Pentium M
   |a1=L<sub>g</sub> |d1=70 nm
+
   |a1=T<sub>ox</sub> |d1=1.4 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
   |a2=T<sub>ox</sub> |d2=1.4 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+
   |a2=V<sub>dd</sub> |d2=1.4 V      |a22=SRAM            |d22=2.45 µm²
   |a3=V<sub>dd</sub> |d3=1.4 V
+
   |a3=L<sub>g</sub> |d3=70 nm
   |a4=SRAM (HD)      |d4=2.45 µm²
+
   |a4=CPP            |d4=336 nm    |a42=MMP            |d42=345 nm
 
}}
 
}}
 
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
 
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
 
   |xtor img=intel 90nm gate.png
 
   |xtor img=intel 90nm gate.png
 
   |archs=Pentium M
 
   |archs=Pentium M
   |a1=L<sub>g</sub> |d1=50 nm
+
   |a1=T<sub>ox</sub> |d1=1.2 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
   |a2=T<sub>ox</sub> |d2=1.2 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
+
   |a2=V<sub>dd</sub> |d2=1.2 V      |a22=SRAM            |d22=1.00 µm²
   |a3=V<sub>dd</sub> |d3=1.2 V
+
   |a3=L<sub>g</sub> |d3=50 nm
   |a4=SRAM (HD)      |d4=1.00 µm²
+
   |a4=CPP            |d4=260 nm    |a42=MMP            |d42=220 nm
 
}}
 
}}
 
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
 
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm

Revision as of 06:24, 11 May 2017

This article details details Intel's Semiconductor Process Technology history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.

Timeline

1 µm vs 500 nm yield
Ramps from 1 µm to 65 nm
SRAM test chips from 130 nm to 45 nm
YearProcessNodeMLayersµarchsTransistorAttributes
CHMOS I 3 µm 1 Tox70 nmGate Dielectric
Vdd5 VSRAM1120 µm²
Lg3.0 µm
CPP7 µmMMP11 µm
CHMOS II 2 µm 1 Tox40 nmGate Dielectric
Vdd5 VSRAM1740 µm²
Lg2.0 µm
CPP5.6 µmMMP8 µm
1982 P646
(CHMOS III)
1.5 µm 1 80286,
80386
Tox25 nmGate DielectricSi2N2O
Vdd5 VSRAM951.7 µm²
Lg1.5 µm
CPP4.0 µmMMP6.4 µm
1987 P648 1.0 µm 2 80486 Lg1,000 nm
Tox? nmGate Dielectric
Vdd? V
1989 P650 0.8 µm 3 80486 Lg800 nm
Tox? nmGate Dielectric
Vdd? V
1993 P852 0.5 µm 4 P5 Lg500 nm
Tox8.0 nmGate Dielectric
Vdd3.3 V
1995 P854 0.35 µm 4 P6 Lg350 nm
Tox5.2 nmGate Dielectric
Vdd2.5 V
1997 P856
P856.5
0.25 µm 5 P6 Lg200 nm
Tox3.1 nmGate DielectricSiO2
Vdd1.8 V
1999 P858 0.18 µm 6 NetBurst Tox2.0 nmGate DielectricSiO2
Vdd1.6 VSRAM5.59 µm²
Lg130 nm
CPP480 nmMMP500 nm
2001 P860 0.13 µm 6 Pentium M Tox1.4 nmGate DielectricSiO2
Vdd1.4 VSRAM2.45 µm²
Lg70 nm
CPP336 nmMMP345 nm
2003 P1262 90 nm 7 Pentium M intel 90nm gate.png Tox1.2 nmGate DielectricSiO2
Vdd1.2 VSRAM1.00 µm²
Lg50 nm
CPP260 nmMMP220 nm
2005 P1264 65 nm 8 Core,
Modified Pentium M
ToxGate DielectricSiO2
VddSRAM0.570 µm²
Lg35 nm
CPP220 nmMMP210 nm
2007 P1266 45 nm 9 Penryn,
Nehalem
ToxGate DielectricHigh-κ
VddSRAM0.346 µm²
Lg25 nm
CPP160 nmMMP180 nm
2009 P1268 32 nm 10 Westmere,
Sandy Bridge
ToxGate DielectricHigh-κ
VddSRAM0.148 µm²
Lg30 nm
CPP112.5 nmMMP112.5 nm
2011 P1270 22 nm 11 Ivy Bridge,
Haswell
ToxGate DielectricHigh-κ
VddSRAM0.092 µm²
Lg26 nm
CPP90 nmMMP80 nm
2014 P1272 14 nm 11 Broadwell,
Skylake,
Kaby Lake,
Coffee Lake
ToxGate DielectricHigh-κ
VddSRAM0.0499 µm²
Lg20 nm
CPP70 nmMMP52 nm
2017 P1274 10 nm Cannonlake,
Icelake,
Tigerlake
ToxGate DielectricHigh-κ
VddSRAM0.0312 µm²
Lg18 nm ?
CPP54 nmMMP36 nm
2019 P1276 7 nm
2022 P1278 5 nm