Editing intel/microarchitectures/whiskey lake

{{intel title|Whiskey Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Whiskey Lake
|designer=Intel
|manufacturer=Intel
|introduction=Q4, 2018
|process=14 nm++
|cores=4
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=5-way
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=256 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=2 MiB
|l3 per=core
|l3 desc=Up to 16-way set associative
|core name=Whiskey Lake U
|predecessor=Kaby Lake
|predecessor link=intel/microarchitectures/kaby lake
|successor=Comet Lake
|successor link=intel/microarchitectures/comet lake
|contemporary=Coffee Lake
|contemporary link=intel/microarchitectures/coffee lake
|contemporary 2=Amber Lake
|contemporary 2 link=intel/microarchitectures/amber lake
|contemporary 3=Cannon Lake
|contemporary 3 link=intel/microarchitectures/cannon lake
}}
'''Whiskey Lake''' ('''WHL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for ultra-low power mobile devices, launched concurrently with {{\\|Coffee Lake}} and {{\\|Amber Lake}}. 

== Codenames ==
{{future information}}


{| class="wikitable"
|-
! Core !! Abbrev !! Description !! Graphics !! Target
|-
| {{intel|Whiskey Lake U|l=core}} || WHL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|}

== Brands ==
{{empty section}}

== Release Dates ==
Whiskey Lake processors are expected to be introduced in the summer of 2018.

== Technology ==
Whiskey Lake is fabricated on 3rd generation improved [[14 nm process|14+++ process]].

== Compatibility ==
{{empty section}}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
|-
| rowspan="5" | {{intel|Whiskey Lake U|U|l=core}}
|-
|| 0 || 0x6 || 0x8 || 0xE || 0xB
|-
| colspan="5" | Family 6 Model 142 Stepping 11
|-
|| 0 || 0x6 || 0x8 || 0xE || 0xC
|-
| colspan="5" | Family 6 Model 142 Stepping 12
|}

== Architecture ==

=== Key changes from {{\\|Kaby Lake}}===

Speculative execution fixes - see https://www.intel.com/content/www/us/en/architecture-and-technology/engineering-new-protections-into-hardware.html

{{future information}}
<!--
* Package and pin-compatible with {{\\|Cannon Lake}} {{intel|Cannon Lake U|U|l=core}}
* Die from {{intel|Coffee Lake U|l=core}} and {{intel|Cannon Point|l=chipset}} PCH
-->

== Overview ==
{{empty section}}

== All Whiskey Lake Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4">
{{comp table header|main|13:List of Whiskey Lake-based Processors}}
{{comp table header|main|10:Main processor|4:Integrated Graphics}}
{{comp table header 1|cols=Launched, Price, Family, %Cores, %Threads, %L3$, TDP, %Frequency, %Turbo, %Max Memory, Name, %Frequency, %Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Whiskey Lake]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Whiskey Lake]]}}
</table>
{{comp table end}}
codename	Whiskey Lake +
core count	4 +
designer	Intel +
first launched	April 2018 +
full page name	intel/microarchitectures/whiskey lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Whiskey Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +