From WikiChip
Tigerlake - Microarchitectures - Intel
< intel‎ | microarchitectures
Revision as of 01:37, 13 December 2017 by David (talk | contribs)

Edit Values
Tigerlake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Instructions
ISAx86-64
Succession

Tigerlake (TGL) is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.

Process Technology

Main article: Cannon Lake § Process Technology

Tigerlake is set to use the same 10 nm process that was designed for Cannon Lake.

Architecture

Not much is known about Tigerlake's architecture.

Key changes from Icelake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


See also

codenameTigerlake +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeCPU +
nameTigerlake +
process10 nm (0.01 μm, 1.0e-5 mm) +