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Difference between revisions of "intel/microarchitectures/tiger lake"
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|process=10 nm
|process=10 nm
|core name=Tiger Lake U
|core name 2=Tiger Lake H
|predecessor=Ice Lake (client)
|predecessor=Ice Lake (client)
|predecessor link=intel/microarchitectures/ice lake (client)
|predecessor link=intel/microarchitectures/ice lake (client)

Revision as of 08:27, 27 August 2020

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Tiger Lake µarch
General Info
Arch TypeCPU
IntroductionSeptember 2, 2020
Process10 nm
Core NamesTiger Lake U,
Tiger Lake H
Sapphire Rapids

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Process Technology

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.


Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.


Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake

  • Core
    • Sunny Cove Willow Cove
    • Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
    • 2,25x larger Level 2 cache - 1,25MB per core from 512KB per core
  • GPU
    • Gen11 Gen12 (Xe)
    • 1.5x more EUs (96, up from 64)
  • Display
    • HDMI 2.1 (from HDMI 2.0b)
  • I/O
    • PCIe 4.0 (from 3.0)
  • Hardware Telemetry
    • Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
codenameTiger Lake +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +