From WikiChip
Difference between revisions of "intel/microarchitectures/tiger lake"
< intel‎ | microarchitectures

(Key changes from {{\\|Ice Lake}}: - per Toms Hardware article today, Tiger Lake will feature up to 3MB LLC per core)
(Key changes from {{\\|Ice Lake}}: Fixed link to Willow Cove.)
Line 31: Line 31:
=== Key changes from {{\\|Ice Lake}}===
=== Key changes from {{\\|Ice Lake}}===
* Core
* Core
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove|l=arch}}
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core

Revision as of 16:13, 29 November 2019

Edit Values
Tiger Lake µarch
General Info
Arch TypeCPU
Process10 nm
Sapphire Rapids

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Process Technology

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's second generation enhanced 10nm+ process.


Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.


Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake

  • Core
  • GPU
    • Gen11 Gen12 (Xe)
    • 1.5x more EUs (96, up from 64)
  • Display
    • HDMI 2.1 (from HDMI 2.0b)
  • I/O
    • PCIe 4.0 (from 3.0)
codenameTiger Lake +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +