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Difference between revisions of "intel/microarchitectures/tiger lake"
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{{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | {{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | ||
Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | ||
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| + | == See also == | ||
| + | * AMD {{amd|Zen+|l=arch}} | ||
Revision as of 23:11, 23 February 2017
| Edit Values | |
| Tigerlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Succession | |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
See also
- AMD Zen+
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tigerlake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tigerlake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
