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Difference between revisions of "intel/microarchitectures/tiger lake"
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|introduction=September 2, 2020
|introduction=September 2, 2020
|process=10 nm
|process=10 nm
|cores 2=4
|cores 3=6
|cores 4=8
|stages min=14
|stages max=19
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=48 KiB
|l1d per=core
|l1d desc=12-way set associative
|l2=1280 KiB
|l2 per=core
|l2 desc=20-way set associative
|l3=3 MiB
|l3 per=core
|l3 desc=12-way set associative
|core name=Tiger Lake U
|core name=Tiger Lake U
|core name 2=Tiger Lake H
|core name 2=Tiger Lake H

Latest revision as of 12:29, 20 June 2021

Edit Values
Tiger Lake µarch
General Info
Arch TypeCPU
IntroductionSeptember 2, 2020
Process10 nm
Core Configs2, 4, 6, 8
Reg RenamingYes
L1I Cache32 KiB/core
8-way set associative
L1D Cache48 KiB/core
12-way set associative
L2 Cache1280 KiB/core
20-way set associative
L3 Cache3 MiB/core
12-way set associative
Core NamesTiger Lake U,
Tiger Lake H
Sapphire Rapids
Rocket Lake

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.


Core Abbrev Description Graphics Target
Tiger Lake Y TGL-Y Extremely low power 2-in-1s detachable, tablets, and computer sticks
Tiger Lake U TGL-U Ultra-low Power Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Tiger Lake H35 TGL-H35 High-performance Graphics 35W TDP. High mobile performance, mobile workstations
Tiger Lake H TGL-H High-performance Graphics 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations

Process Technology[edit]

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.


Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.


Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake[edit]

  • Core
    • Sunny Cove Willow Cove
    • Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
    • 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
  • GPU
    • Gen11 Gen12 (Xe)
    • 1.5x more EUs (96, up from 64)
  • Display
    • HDMI 2.1 (from HDMI 2.0b)
  • I/O
    • PCIe 4.0 (from 3.0)
  • Hardware Telemetry
    • Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
codenameTiger Lake +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +