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{{intel title|Tigerlake|arch}}
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{{intel title|Tiger Lake|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
|name=Tigerlake
+
|name=Tiger Lake
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|introduction=2019
+
|introduction=September 2, 2020
 
|process=10 nm
 
|process=10 nm
 
|isa=x86-64
 
|isa=x86-64
|predecessor=Ice Lake
+
|core name=Tiger Lake U
|predecessor link=intel/microarchitectures/ice lake
+
|core name 2=Tiger Lake H
 +
|predecessor=Ice Lake (client)
 +
|predecessor link=intel/microarchitectures/ice lake (client)
 
|successor=Alder Lake
 
|successor=Alder Lake
 
|successor link=intel/microarchitectures/alder lake
 
|successor link=intel/microarchitectures/alder lake
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|succession=Yes
 
|succession=Yes
 
}}
 
}}
'''Tigerlake''' ('''TGL''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Icelake}}. Tigerlake is expected to be fabricated using a [[10 nm process]]. Tigerlake is the "Optimization" microarchitecture as part of Intel's {{intel|PAO}} model.
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'''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, a [[10 nm process|10nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices.
  
 
== Process Technology==
 
== Process Technology==
 
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}
 
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}
Tigerlake is set to use the same [[10 nm process]] that was designed for Cannon Lake.
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Tiger Lake will be manufactured on Intel's third generation enhanced [[10 nm process|10nm++ process]].
 +
 
 +
== History ==
 +
[[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]]
 +
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.
  
 
== Architecture ==
 
== Architecture ==
Not much is known about Tigerlake's architecture.
+
Not much is known about Tiger Lake's architecture.
 
 
=== Key changes from {{\\|Icelake}}===
 
{{future information}}
 
 
 
* {{intel|Gen11|l=arch}} → {{intel|Gen12|l=arch}} graphics
 
 
 
  
== See also ==
+
=== Key changes from {{\\|Ice Lake}}===
 +
* Core
 +
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}
 +
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
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** 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
 +
* GPU
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** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe)
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** 1.5x more EUs (96, up from 64)
 +
* Display
 +
** [[HDMI]] 2.1 (from HDMI 2.0b)
 +
* I/O
 +
** PCIe 4.0 (from 3.0)
 +
* Hardware Telemetry
 +
** Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.

Latest revision as of 20:17, 26 September 2020

Edit Values
Tiger Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionSeptember 2, 2020
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesTiger Lake U,
Tiger Lake H
Succession
Contemporary
Sapphire Rapids

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Process Technology[edit]

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.

History[edit]

Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.

Architecture[edit]

Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake[edit]

  • Core
    • Sunny Cove Willow Cove
    • Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
    • 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
  • GPU
    • Gen11 Gen12 (Xe)
    • 1.5x more EUs (96, up from 64)
  • Display
    • HDMI 2.1 (from HDMI 2.0b)
  • I/O
    • PCIe 4.0 (from 3.0)
  • Hardware Telemetry
    • Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
codenameTiger Lake +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +