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Difference between revisions of "intel/microarchitectures/tiger lake"
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{{intel title|Tigerlake|arch}}
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{{intel title|Tiger Lake|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
|name=Tigerlake
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|name=Tiger Lake
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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== Process Technology==
 
== Process Technology==
 
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}
 
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}
Tigerlake is set to use the same [[10 nm process]] that was designed for Cannon Lake.
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Tiger Lake is set to use the same [[10 nm process]] that was designed for Cannon Lake.
  
 
== Architecture ==
 
== Architecture ==
Not much is known about Tigerlake's architecture.
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Not much is known about Tiger Lake's architecture.
  
=== Key changes from {{\\|Icelake}}===
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=== Key changes from {{\\|Ice Lake}}===
 
{{future information}}
 
{{future information}}
  
 
* {{intel|Gen11|l=arch}} → {{intel|Gen12|l=arch}} graphics
 
* {{intel|Gen11|l=arch}} → {{intel|Gen12|l=arch}} graphics
 
 
== See also ==
 

Revision as of 02:02, 6 April 2018

Edit Values
Tiger Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Instructions
ISAx86-64
Succession
Contemporary
Sapphire Rapids

Tiger Lake (TGL) is Intel's successor to Ice Lake, an enhanced 10nm+ process microarchitecture for mainstream workstations, desktops, and mobile devices.

Process Technology

Main article: Cannon Lake § Process Technology

Tiger Lake is set to use the same 10 nm process that was designed for Cannon Lake.

Architecture

Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
codenameTiger Lake +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +