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Revision as of 22:41, 5 April 2018
Tigerlake (TGL) is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
- Main article: Cannon Lake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannon Lake.
Not much is known about Tigerlake's architecture.
Key changes from Icelake
|Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.|
|first launched||2019 +|
|full page name||intel/microarchitectures/tiger lake +|
|instance of||microarchitecture +|
|instruction set architecture||x86-64 +|
|microarchitecture type||CPU +|
|process||10 nm (0.01 μm, 1.0e-5 mm) +|