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'''Tigerlake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Icelake}}. Tigerlake is expected to be fabricated using a [[10 nm process]]. Tigerlake is the "Optimization" microarchitecture as part of Intel's {{intel|PAO}} model.
 
'''Tigerlake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Icelake}}. Tigerlake is expected to be fabricated using a [[10 nm process]]. Tigerlake is the "Optimization" microarchitecture as part of Intel's {{intel|PAO}} model.
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== Process Technology==
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{{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}}
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Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake.

Revision as of 07:01, 16 September 2016

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Tigerlake µarch
General Info
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Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.

Process Technology

Main article: Cannonlake § Process Technology

Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.

codenameTiger Lake +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +