Revision history of "intel/microarchitectures/tiger lake"

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(cur | prev) 10:46, 19 July 2023‎ 213.175.37.10 (talk)‎ . . (2,962 bytes) (+96)‎ . . (→‎Key changes from {{\\|Ice Lake}}) (undo)
(cur | prev) 12:29, 20 June 2021‎ 173.244.217.55 (talk)‎ . . (2,866 bytes) (+12)‎ . . (undo)
(cur | prev) 12:26, 20 June 2021‎ 179.213.246.113 (talk)‎ . . (2,854 bytes) (+16)‎ . . (undo)
(cur | prev) 12:25, 20 June 2021‎ 179.213.246.113 (talk)‎ . . (2,838 bytes) (+47)‎ . . (undo)
(cur | prev) 12:21, 20 June 2021‎ 179.213.246.113 (talk)‎ . . (2,791 bytes) (-4)‎ . . (undo)
(cur | prev) 12:20, 20 June 2021‎ 179.213.246.113 (talk)‎ . . (2,795 bytes) (+286)‎ . . (undo)
(cur | prev) 10:12, 24 May 2021‎ 86.127.244.44 (talk)‎ . . (2,509 bytes) (-4)‎ . . (undo)
(cur | prev) 04:50, 13 January 2021‎ 111.107.210.162 (talk)‎ . . (2,513 bytes) (+656)‎ . . (undo)
(cur | prev) 08:13, 12 January 2021‎ 111.107.210.162 (talk)‎ . . (1,857 bytes) (+86)‎ . . (undo)
(cur | prev) 21:17, 26 September 2020‎ 79.245.174.215 (talk)‎ . . (1,771 bytes) (-1)‎ . . (1.25 MB / 512 KB = 2.5, not 2.25) (undo)
(cur | prev) 08:27, 27 August 2020‎ 188.127.171.163 (talk)‎ . . (1,772 bytes) (+50)‎ . . (undo)
(cur | prev) 17:54, 5 August 2020‎ 115.134.19.132 (talk)‎ . . (1,722 bytes) (+13)‎ . . (https://www.intc.com/investor-relations/events-and-presentations/events-calendar/event-details/2020/Tiger-Lake-Launch/default.aspx "Tiger Lake Virtual Launch Event September 2, 2020") (undo)
(cur | prev) 11:33, 24 June 2020‎ 188.127.163.45 (talk)‎ . . (1,709 bytes) (+68)‎ . . (added L2 info) (undo)
(cur | prev) 21:44, 8 May 2020‎ 13.248.98.34 (talk)‎ . . (1,641 bytes) (+129)‎ . . (undo)
(cur | prev) 12:11, 17 December 2019‎ 188.127.166.94 (talk)‎ . . (1,512 bytes) (0)‎ . . (corrected number of pluses) (undo)
(cur | prev) 16:13, 29 November 2019‎ 82.25.98.106 (talk)‎ . . (1,512 bytes) (-7)‎ . . (→‎Key changes from {{\\|Ice Lake}}: Fixed link to Willow Cove.) (undo)
(cur | prev) 06:55, 17 September 2019‎ 62.254.184.4 (talk)‎ . . (1,519 bytes) (+67)‎ . . (→‎Key changes from {{\\|Ice Lake}}: - per Toms Hardware article today, Tiger Lake will feature up to 3MB LLC per core) (undo)
(cur | prev) 03:38, 11 August 2019‎ 110.159.135.217 (talk)‎ . . (1,452 bytes) (+72)‎ . . (https://www.fanlesstech.com/2019/08/the-2021-gaming-nuc-is-already-in-works.html) (undo)
(cur | prev) 09:08, 28 May 2019‎ 82.130.11.72 (talk)‎ . . (1,380 bytes) (0)‎ . . (→‎History: ? Roadmap says 2020, linked article says 2020, but this wiki page says 2021?) (undo)
(cur | prev) 21:22, 12 May 2019‎ David (talk | contribs)‎ . . (1,380 bytes) (+16)‎ . . (→‎Key changes from {{\\|Ice Lake}}) (undo)
(cur | prev) 21:21, 12 May 2019‎ David (talk | contribs)‎ . . (1,364 bytes) (+303)‎ . . (undo)
(cur | prev) 20:42, 12 May 2019‎ David (talk | contribs)‎ . . (1,061 bytes) (-10)‎ . . (undo)
(cur | prev) 18:54, 3 February 2019‎ David (talk | contribs)‎ . . (1,071 bytes) (0)‎ . . (undo)
(cur | prev) 18:54, 3 February 2019‎ David (talk | contribs)‎ . . (1,071 bytes) (0)‎ . . (undo)
(cur | prev) 16:49, 3 February 2019‎ 122.57.53.251 (talk)‎ . . (1,071 bytes) (0)‎ . . (undo)
(cur | prev) 03:57, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (1,071 bytes) (-20)‎ . . (undo)
(cur | prev) 02:04, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (1,091 bytes) (+18)‎ . . (undo)
(cur | prev) 02:03, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (1,073 bytes) (+26)‎ . . (→‎Process Technology) (undo)
(cur | prev) 02:03, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (1,047 bytes) (+1)‎ . . (undo)
(cur | prev) 02:02, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (1,046 bytes) (-12)‎ . . (undo)
(cur | prev) 23:49, 5 April 2018‎ ChipIt (talk | contribs)‎ m . . (1,058 bytes) (0)‎ . . (ChipIt moved page intel/microarchitectures/tigerlake to intel/microarchitectures/tiger lake) (undo)
(cur | prev) 23:49, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (1,058 bytes) (-49)‎ . . (undo)
(cur | prev) 23:41, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (1,107 bytes) (+81)‎ . . (undo)
(cur | prev) 01:37, 13 December 2017‎ David (talk | contribs)‎ . . (1,026 bytes) (+3)‎ . . (undo)
(cur | prev) 19:40, 30 November 2017‎ Mys 721tx (talk | contribs)‎ . . (1,023 bytes) (+13)‎ . . (undo)
(cur | prev) 09:34, 28 September 2017‎ At32Hz (talk | contribs)‎ . . (1,010 bytes) (-69)‎ . . (undo)
(cur | prev) 17:44, 14 July 2017‎ 60.49.33.29 (talk)‎ . . (1,079 bytes) (+169)‎ . . (https://www.fool.com/investing/2017/07/14/key-detail-of-intel-corporation-tiger-lake-process.aspx "Per a LinkedIn profile of a current Intel employee, the company's Tiger Lake family of processors will include the company's Gen. 12 graphics architecture.") (undo)
(cur | prev) 14:18, 9 June 2017‎ David (talk | contribs)‎ . . (910 bytes) (+12)‎ . . (undo)
(cur | prev) 16:10, 6 March 2017‎ David (talk | contribs)‎ . . (898 bytes) (+1)‎ . . (undo)
(cur | prev) 23:11, 23 February 2017‎ David (talk | contribs)‎ . . (897 bytes) (+42)‎ . . (undo)
(cur | prev) 19:20, 21 January 2017‎ David (talk | contribs)‎ . . (855 bytes) (+25)‎ . . (undo)
(cur | prev) 08:01, 16 September 2016‎ David (talk | contribs)‎ . . (830 bytes) (+210)‎ . . (undo)
(cur | prev) 07:59, 16 September 2016‎ David (talk | contribs)‎ . . (620 bytes) (+90)‎ . . (undo)
(cur | prev) 03:33, 3 August 2016‎ David (talk | contribs)‎ . . (530 bytes) (-20)‎ . . (undo)
(cur | prev) 10:11, 30 June 2016‎ At32Hz (talk | contribs)‎ . . (550 bytes) (-5)‎ . . (undo)
(cur | prev) 19:14, 16 May 2016‎ ChipIt (talk | contribs)‎ . . (555 bytes) (+27)‎ . . (undo)
(cur | prev) 00:35, 15 April 2016‎ At32Hz (talk | contribs)‎ m . . (528 bytes) (0)‎ . . (At32Hz moved page intel/microarchitectures/Tigerlake to intel/microarchitectures/tigerlake: typo) (undo)
(cur | prev) 00:34, 15 April 2016‎ At32Hz (talk | contribs)‎ . . (528 bytes) (+528)‎ . . (Created page with "{{intel title|Tigerlake|arch}} {{microarchitecture | name = Tigerlake | manufacturer = Intel | introduction = 2019-2020 | phase-out = | process...")

codename	Tiger Lake +
core count	2 +, 4 +, 6 + and 8 +
designer	Intel +
first launched	September 2, 2020 +
full page name	intel/microarchitectures/tiger lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Tiger Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	10 nm (0.01 μm, 1.0e-5 mm) +

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