Editing intel/microarchitectures/tiger lake

{{intel title|Tiger Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Tiger Lake
|designer=Intel
|manufacturer=Intel
|introduction=September 2, 2020
|process=10 nm
|cores=2
|cores 2=4
|cores 3=6
|cores 4=8
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=5-way
|isa=x86-64
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=48 KiB
|l1d per=core
|l1d desc=12-way set associative
|l2=1280 KiB
|l2 per=core
|l2 desc=20-way set associative
|l3=3 MiB
|l3 per=core
|l3 desc=12-way set associative
|core name=Tiger Lake U
|core name 2=Tiger Lake H
|predecessor=Ice Lake (client)
|predecessor link=intel/microarchitectures/ice lake (client)
|successor=Alder Lake
|successor link=intel/microarchitectures/alder lake
|contemporary=Sapphire Rapids
|contemporary link=intel/microarchitectures/sapphire rapids
|contemporary 2=Rocket Lake
|contemporary 2 link=intel/microarchitectures/rocket lake
|succession=Yes
}}
'''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, a [[10 nm process|10nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Description !! Graphics !! Target
|-
| {{intel|Tiger Lake Y|l=core}} || TGL-Y || Extremely low power ||  || 2-in-1s detachable, tablets, and computer sticks
|-
| {{intel|Tiger Lake U|l=core}} || TGL-U || Ultra-low Power || || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|-
| {{intel|Tiger Lake H35|l=core}} || TGL-H35 || High-performance Graphics || || 35W TDP. High mobile performance, mobile workstations
|-
| {{intel|Tiger Lake H|l=core}} || TGL-H || High-performance Graphics || || 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations
|}

== Process Technology==
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}
Tiger Lake will be manufactured on Intel's third generation enhanced [[10 nm process|10nm++ process]].

== History ==
[[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]]
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.

== Architecture ==
Not much is known about Tiger Lake's architecture.

=== Key changes from {{\\|Ice Lake}}===
* Core
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}
*** Implemented POP to PUSH data forwarding, reg->reg and imm->reg (~1 PUSH+POP pair per cycle)
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
** 2,25x larger Level 2 cache - 1,25MB per core from 512KB per core
* GPU
** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe)
** 1.5x more EUs (96, up from 64)
* Display
** [[HDMI]] 2.1 (from HDMI 2.0b)
* I/O
** PCIe 4.0 (from 3.0)
* Hardware Telemetry
** Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
codename	Tiger Lake +
core count	2 +, 4 +, 6 + and 8 +
designer	Intel +
first launched	September 2, 2020 +
full page name	intel/microarchitectures/tiger lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Tiger Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	10 nm (0.01 μm, 1.0e-5 mm) +