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{{see also|intel/microarchitectures/skylake_(client)#Die|l1=Client Skylake's Die}} | {{see also|intel/microarchitectures/skylake_(client)#Die|l1=Client Skylake's Die}} | ||
[[File:intel xeon skylake sp.jpg|right|300px|thumb|Skylake SP chips and wafer.]] | [[File:intel xeon skylake sp.jpg|right|300px|thumb|Skylake SP chips and wafer.]] | ||
− | Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: | + | Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: Low Core Count (LCC), High Core Count (HCC), and Extreme Core Count (XCC). |
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=== Core Tile === | === Core Tile === | ||
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=== Low Core Count (LCC) === | === Low Core Count (LCC) === | ||
* [[14 nm process]] | * [[14 nm process]] | ||
− | * | + | * ? metal layers |
* ~22.26 mm x ~14.62 mm | * ~22.26 mm x ~14.62 mm | ||
* ~325.44 mm² die size | * ~325.44 mm² die size | ||
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− | : (NOT official die shot, artist's rendering based on the larger | + | |
+ | : (NOT official die shot, artist's rendering based on the larger dies) | ||
: [[File:skylake lcc die shot.jpg|650px]] | : [[File:skylake lcc die shot.jpg|650px]] | ||
Facts about "Skylake (server) - Microarchitectures - Intel"
codename | Skylake (server) + |
core count | 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 + and 28 + |
designer | Intel + |
first launched | May 4, 2017 + |
full page name | intel/microarchitectures/skylake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |