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== Architecture == | == Architecture == | ||
− | Sandy Bridge features an entirely new architecture with a brand new core design which is both more | + | Sandy Bridge's features an entirely new architecture with a brand new core design which is both more performent and more power efficient. The front-end has been entirely rearchitected to incorporate a new decoded pipeline using a new µOP cache. The back-end is an entirely new PRF-based renaming architecture with a considerably large parallelism window. Sandy Bridge also provides considerable higher integration verses its {{intel|microarchitectures|predecessors}} resulting a full [[system on a chip]] design. |
=== Key changes from {{\\|Westmere}} === | === Key changes from {{\\|Westmere}} === | ||
[[File:sandy bridge buffer window.png|right|350px]] | [[File:sandy bridge buffer window.png|right|350px]] |
Facts about "Sandy Bridge (client) - Microarchitectures - Intel"
codename | Sandy Bridge (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | September 13, 2010 + |
full page name | intel/microarchitectures/sandy bridge (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Sandy Bridge (client) + |
phase-out | November 2012 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |