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{{intel title|Rocket Lake|arch}}
 
{{intel title|Rocket Lake|arch}}
 
{{microarchitecture
 
{{microarchitecture
|atype=CPU
+
|atype=APU
 
|name=Rocket Lake
 
|name=Rocket Lake
 
|designer=Intel
 
|designer=Intel
Line 7: Line 7:
 
|process=14 nm
 
|process=14 nm
 
|cores=4
 
|cores=4
|cores 5=6
+
|cores 2=6
|cores 9=8
+
|cores 3=8
|cores 13=10
 
 
|type=Superscalar
 
|type=Superscalar
 
|type 2=Superpipeline
 
|type 2=Superpipeline
Line 55: Line 54:
 
|l1d per=core
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
|l2= 1280 KiB
+
|l2=512 KiB
 
|l2 per=core
 
|l2 per=core
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
|l3=3 MiB
+
|l3=2 MiB
 
|l3 per=core
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
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|l4 per=package
 
|l4 per=package
 
|l4 desc=on Iris Pro GPUs only
 
|l4 desc=on Iris Pro GPUs only
 +
|core name=Cypress Cove
 
|predecessor=Comet Lake
 
|predecessor=Comet Lake
 
|predecessor link=intel/microarchitectures/comet lake
 
|predecessor link=intel/microarchitectures/comet lake
 +
|successor=Alder Lake
 +
|successor link=intel/microarchitectures/alder_lake
 +
|contemporary=Tiger Lake
 +
|contemporary link=intel/microarchitectures/tiger_lake
 
}}
 
}}
 
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.
 
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.
Line 81: Line 85:
  
 
== Brands ==
 
== Brands ==
Intel is expected to release Comet Lake under 3 main brand families:
+
Intel is expected to release Rocket Lake under 3 main brand families:
  
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
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== Release Dates ==
 
== Release Dates ==
Rocket Lake is expected to be released in Q4 2020 or Q1 2021.
+
Rocket Lake is expected to be released in Q1 2021.
  
 
== Compatibility==
 
== Compatibility==
 
{{empty section}}
 
{{empty section}}
 +
Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with [[Comet Lake]]. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.
  
 
== Compiler support ==
 
== Compiler support ==
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! Compiler !! Arch-Specific || Arch-Favorable
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
+
| [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code>
 
|-
 
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
+
| [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code>
 
|-
 
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
+
| [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code>
 
|-
 
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
+
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/?</code>
 
|}
 
|}
  
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== Architecture ==
 
== Architecture ==
=== Key changes from {{\\|Coffee Lake}}===
+
=== Key changes from {{\\|Comet Lake}}===
{{empty section}}
+
{{future information}}
 +
* Core
 +
** {{\\|Skylake}} '''➡''' {{\\|Cypress Cove}}
 +
 
 +
* GPU
 +
** {{intel|Gen 9.5|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe)
 +
** 32 EUs up from 24 EUs
 +
 
 +
* Display
 +
** [[DisplayPort]] 1.4a (from DisplayPort 1.2)
 +
** [[HDMI]] 2.0b (from HDMI 1.4b)
 +
 
 +
* I/O
 +
** PCIe 4.0 (from 3.0)
 +
 
 +
* Memory
 +
** Faster memory for mainstream desktops (i.e., {{intel|Rocket Lake S|l=core}}) DDR4-3200 (from DDR4-2933)
 +
 
 +
* Chipset
 +
** {{intel|Cannon Point|400 Series chipset|l=chipset}} → {{intel|Rocket Point|500 Series chipset|l=chipset}}
 +
*** 2.5G Ethernet (Foxville) support
 +
*** Integrated WiFi 6 AX201 (GiG+) support via {{intel|CNVi}}
 +
 
 +
* Packaging
 +
** [[Die thinning]] on top-end SKUs for better heat removal
  
 
== See also ==
 
== See also ==
* AMD {{amd|Zen 2|l=arch}}
 

Revision as of 07:40, 3 February 2021

Edit Values
Rocket Lake µarch
General Info
Arch TypeAPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs4, 6, 8
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache48 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache512 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
L4 Cache128 MiB/package
on Iris Pro GPUs only
Cores
Core NamesCypress Cove
Succession
Contemporary
Tiger Lake

Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.


Codenames

Core Description Graphics Target
Rocket Lake S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Rocket Lake U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands

Intel is expected to release Rocket Lake under 3 main brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 TBT ECC
core i3 logo (2015).png Core i3 Low-end Performance
core i5 logo (2015).png Core i5 Mid-range Performance
core i7 logo (2015).png Core i7 High-end Performance

Release Dates

Rocket Lake is expected to be released in Q1 2021.

Compatibility

New text document.svg This section is empty; you can help add the missing info by editing this page.

Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with Comet Lake. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.

Compiler support

Compiler Arch-Specific Arch-Favorable
ICC -march=? -mtune=?
GCC -march=? -mtune=?
LLVM -march=? -mtune=?
Visual Studio /arch:AVX2 /?

CPUID

New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture

Key changes from Comet Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Display
  • I/O
    • PCIe 4.0 (from 3.0)
  • Memory
    • Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2933)
  • Packaging

See also

codenameRocket Lake +
core count4 +, 6 + and 8 +
designerIntel +
full page nameintel/microarchitectures/rocket lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
nameRocket Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +