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Difference between revisions of "intel/microarchitectures/rocket lake"
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{{intel title|Rocket Lake|arch}} | {{intel title|Rocket Lake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype= | + | |atype=APU |
|name=Rocket Lake | |name=Rocket Lake | ||
|designer=Intel | |designer=Intel | ||
Line 7: | Line 7: | ||
|process=14 nm | |process=14 nm | ||
|cores=4 | |cores=4 | ||
+ | |cores 2=6 | ||
+ | |cores 3=8 | ||
|type=Superscalar | |type=Superscalar | ||
|type 2=Superpipeline | |type 2=Superpipeline | ||
Line 46: | Line 48: | ||
|extension 29=SGX | |extension 29=SGX | ||
|extension 30=MPX | |extension 30=MPX | ||
− | |l1i= | + | |l1i=48 KiB |
|l1i per=core | |l1i per=core | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
Line 52: | Line 54: | ||
|l1d per=core | |l1d per=core | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l2= | + | |l2=512 KiB |
|l2 per=core | |l2 per=core | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
Line 61: | Line 63: | ||
|l4 per=package | |l4 per=package | ||
|l4 desc=on Iris Pro GPUs only | |l4 desc=on Iris Pro GPUs only | ||
+ | |core name=Cypress Cove | ||
|predecessor=Comet Lake | |predecessor=Comet Lake | ||
|predecessor link=intel/microarchitectures/comet lake | |predecessor link=intel/microarchitectures/comet lake | ||
+ | |successor=Alder Lake | ||
+ | |successor link=intel/microarchitectures/alder_lake | ||
+ | |contemporary=Tiger Lake | ||
+ | |contemporary link=intel/microarchitectures/tiger_lake | ||
}} | }} | ||
− | '''Rocket Lake''' is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices. | + | '''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices. |
+ | |||
+ | |||
+ | == Codenames == | ||
+ | {| class="wikitable" | ||
+ | |- | ||
+ | ! Core !! Description !! Graphics !! Target | ||
+ | |- | ||
+ | | {{intel|Rocket Lake S|l=core}} || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis | ||
+ | |- | ||
+ | | {{intel|Rocket Lake U|l=core}} || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | ||
+ | |} | ||
+ | |||
+ | == Brands == | ||
+ | Intel is expected to release Rocket Lake under 3 main brand families: | ||
+ | |||
+ | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
+ | |- | ||
+ | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features | ||
+ | |- | ||
+ | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
+ | |- | ||
+ | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || || | ||
+ | |- | ||
+ | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || || | ||
+ | |- | ||
+ | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || || | ||
+ | |} | ||
+ | |||
+ | == Release Dates == | ||
+ | Rocket Lake is expected to be released in Q1 2021. | ||
+ | |||
+ | == Compatibility== | ||
+ | {{empty section}} | ||
+ | Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with [[Comet Lake]]. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake. | ||
+ | |||
+ | == Compiler support == | ||
+ | {| class="wikitable" | ||
+ | |- | ||
+ | ! Compiler !! Arch-Specific || Arch-Favorable | ||
+ | |- | ||
+ | | [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code> | ||
+ | |- | ||
+ | | [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code> | ||
+ | |- | ||
+ | | [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code> | ||
+ | |- | ||
+ | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/?</code> | ||
+ | |} | ||
+ | |||
+ | === CPUID === | ||
+ | {{empty section}} | ||
+ | |||
+ | == Architecture == | ||
+ | === Key changes from {{\\|Comet Lake}}=== | ||
+ | {{future information}} | ||
+ | * Core | ||
+ | ** {{\\|Skylake}} '''➡''' {{\\|Cypress Cove}} | ||
+ | |||
+ | * GPU | ||
+ | ** {{intel|Gen 9.5|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe) | ||
+ | ** 32 EUs up from 24 EUs | ||
+ | |||
+ | * Display | ||
+ | ** [[DisplayPort]] 1.4a (from DisplayPort 1.2) | ||
+ | ** [[HDMI]] 2.0b (from HDMI 1.4b) | ||
+ | |||
+ | * I/O | ||
+ | ** PCIe 4.0 (from 3.0) | ||
+ | |||
+ | * Memory | ||
+ | ** Faster memory for mainstream desktops (i.e., {{intel|Rocket Lake S|l=core}}) DDR4-3200 (from DDR4-2933) | ||
+ | |||
+ | * Chipset | ||
+ | ** {{intel|Cannon Point|400 Series chipset|l=chipset}} → {{intel|Rocket Point|500 Series chipset|l=chipset}} | ||
+ | *** 2.5G Ethernet (Foxville) support | ||
+ | *** Integrated WiFi 6 AX201 (GiG+) support via {{intel|CNVi}} | ||
+ | |||
+ | * Packaging | ||
+ | ** [[Die thinning]] on top-end SKUs for better heat removal | ||
+ | |||
+ | == See also == |
Revision as of 07:40, 3 February 2021
Edit Values | |
Rocket Lake µarch | |
General Info | |
Arch Type | APU |
Designer | Intel |
Manufacturer | Intel |
Process | 14 nm |
Core Configs | 4, 6, 8 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
Cache | |
L1I Cache | 48 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 512 KiB/core 4-way set associative |
L3 Cache | 2 MiB/core Up to 16-way set associative |
L4 Cache | 128 MiB/package on Iris Pro GPUs only |
Cores | |
Core Names | Cypress Cove |
Succession | |
Contemporary | |
Tiger Lake |
Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.
Contents
Codenames
Core | Description | Graphics | Target |
---|---|---|---|
Rocket Lake S | Mainstream performance | GT2 | Desktop performance to value, AiOs, and minis |
Rocket Lake U | Ultra-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands
Intel is expected to release Rocket Lake under 3 main brand families:
Logo | Family | General Description | Differentiating Features | |||||
---|---|---|---|---|---|---|---|---|
Cores | HT | AVX | AVX2 | TBT | ECC | |||
Core i3 | Low-end Performance | |||||||
Core i5 | Mid-range Performance | |||||||
Core i7 | High-end Performance |
Release Dates
Rocket Lake is expected to be released in Q1 2021.
Compatibility
This section is empty; you can help add the missing info by editing this page. |
Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with Comet Lake. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.
Compiler support
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=? |
-mtune=?
|
GCC | -march=? |
-mtune=?
|
LLVM | -march=? |
-mtune=?
|
Visual Studio | /arch:AVX2 |
/?
|
CPUID
This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from Comet Lake
- Core
- Display
- DisplayPort 1.4a (from DisplayPort 1.2)
- HDMI 2.0b (from HDMI 1.4b)
- I/O
- PCIe 4.0 (from 3.0)
- Memory
- Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2933)
- Chipset
- 400 Series chipset → 500 Series chipset
- 2.5G Ethernet (Foxville) support
- Integrated WiFi 6 AX201 (GiG+) support via CNVi
- 400 Series chipset → 500 Series chipset
- Packaging
- Die thinning on top-end SKUs for better heat removal
See also
Facts about "Rocket Lake - Microarchitectures - Intel"
codename | Rocket Lake + |
core count | 4 +, 6 + and 8 + |
designer | Intel + |
full page name | intel/microarchitectures/rocket lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
name | Rocket Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |