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Difference between revisions of "intel/microarchitectures/palm cove"
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(Overview)
(Key changes from {{\\|Skylake (Server)}})
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== Architecture ==
 
== Architecture ==
=== Key changes from {{\\|Skylake (Server)}}===
+
=== Key changes from {{\\|Skylake (Client)}}===
 
* [[10 nm process]] (From [[14 nm]])
 
* [[10 nm process]] (From [[14 nm]])
 +
* Core
 +
** Execution units
 +
*** New 512-bit FMA unit
 +
*** New iDIV unit
 
{{expand list}}
 
{{expand list}}
  

Revision as of 13:12, 9 May 2019

Edit Values
Palm Cove µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018
Process10 nm
Instructions
ISAx86-64
Succession

Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.

Process Technology

Palm Cove is designed to take advantage of Intel's 10 nm process.

Architecture

Key changes from Skylake (Client)

This list is incomplete; you can help by expanding it.

New instructions

Cannon Lake introduced a number of new instructions:

Overview

Palm Cove is the core microarchitecture that is found in Intel's Cannon Lake SoCs. Although originally intended to be mass manufactured for all client and server markets, due to Intel's prolong 10 nm process problems, Palm Cove is getting skipped with the exception of a single chip.

See also

codenamePalm Cove +
designerIntel +
first launched2018 +
full page nameintel/microarchitectures/palm cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
namePalm Cove +
process10 nm (0.01 μm, 1.0e-5 mm) +