From WikiChip
Difference between revisions of "intel/microarchitectures/lakefield"
< intel‎ | microarchitectures

Line 33: Line 33:
 
** LPDDR4X up to 4266 MT/s
 
** LPDDR4X up to 4266 MT/s
 
** POP DRAM
 
** POP DRAM
 +
 +
=== Block diagram ===
 +
{{empty section}}
  
 
== Overview ==
 
== Overview ==
 
{{empty section}}
 
{{empty section}}

Revision as of 10:51, 10 May 2019

Edit Values
Lakefield µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process22 nm, 10 nm
Core Configs5
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
Cache
L2 Cache512 KiB + 1.5 MiB
L3 Cache4 MiB/chip

Lakefield (LKF) is a high-performance low-power 3D microarchitecture designed by Intel and introduced in 2019.

Architecture

Block diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview

New text document.svg This section is empty; you can help add the missing info by editing this page.
codenameLakefield +
core count5 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/lakefield +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameLakefield +
process22 nm (0.022 μm, 2.2e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +