From WikiChip
Difference between revisions of "intel/microarchitectures/knights landing"
< intel‎ | microarchitectures

(Architecture)
Line 28: Line 28:
  
 
== Architecture ==
 
== Architecture ==
 +
=== Key changes from {{\\|Knights Corner}} ===
 
{{empty section}}
 
{{empty section}}
 +
==== New instructions ====
 +
Knights Landing introduced a number of {{x86|extensions|new instructions}}:
 +
 +
* {{x86|AVX-512|<code>AVX-512</code>}}, specifically:
 +
** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation
 +
** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection
 +
** {{x86|AVX512BW|<code>AVX512PF</code>}} - Prefetch instructions for gather/scatter
 +
** {{x86|AVX512DQ|<code>AVX512ER</code>}} - Exponential and Reciprocal Instructions
  
 
== Die ==
 
== Die ==

Revision as of 17:31, 9 March 2018

Edit Values
Knights Landing µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-16, x86-32, x86-64
Succession
Contemporary
Knights Mill

Knights Landing (KNH) is a many-core microarchitecture, produced by intel for high performance computing.

Process Technology

See also: Broadwell § Process Technology and 14 nm lithography process

Knights Landing is fabricated on Intel's 14 nm process.

Architecture

Key changes from Knights Corner

New text document.svg This section is empty; you can help add the missing info by editing this page.

New instructions

Knights Landing introduced a number of new instructions:

  • AVX-512, specifically:
    • AVX512F - AVX-512 Foundation
    • AVX512CD - AVX-512 Conflict Detection
    • AVX512PF - Prefetch instructions for gather/scatter
    • AVX512ER - Exponential and Reciprocal Instructions

Die

Die shot of intel xeon phi, Knights Landing.

  • 14 nm process
  • 682.6 mm² die size
  • 72 CPU cores
  • 7,100,000,000 transistors

intel xeon phi knightslanding die shot .jpeg

codenameKnights Landing +
designerIntel +
full page nameintel/microarchitectures/knights landing +
instance ofmicroarchitecture +
instruction set architecturex86-16 +, x86-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameKnights Landing +
process14 nm (0.014 μm, 1.4e-5 mm) +