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All parts incorporate 4 GiB of [[HBM 2]] along with an [[AMD]] {{amd|Vega|l=arch}} GPU. The HBM2 and GPU are interconnected using Intel's [[EMIB]], however, the CPU and GPU are connected using standard in-package wires over standard PCIe 3.0. x8 lanes are permanently reserved for direct GPU-CPU communication. This leaves x8 additional lanes for all other peripherals that need direct connection to the CPU. | All parts incorporate 4 GiB of [[HBM 2]] along with an [[AMD]] {{amd|Vega|l=arch}} GPU. The HBM2 and GPU are interconnected using Intel's [[EMIB]], however, the CPU and GPU are connected using standard in-package wires over standard PCIe 3.0. x8 lanes are permanently reserved for direct GPU-CPU communication. This leaves x8 additional lanes for all other peripherals that need direct connection to the CPU. | ||
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Intel claims that the use of HBM2 instead of [[GDDR5]] results in 80% less power. It's worth noting that since those are {{intel|Kaby Lake H|l=core}} parts with {{amd|Radeon}} Graphics, they effectively have two GPUs and both GPUs are usable. Fairly significant power saving can be achieved by defaulting to the integrated graphics when high performance is not required. In total there are 3 display outputs from the integrated graphics and an additional 6 outputs from the Radeon graphics for a total of 9. | Intel claims that the use of HBM2 instead of [[GDDR5]] results in 80% less power. It's worth noting that since those are {{intel|Kaby Lake H|l=core}} parts with {{amd|Radeon}} Graphics, they effectively have two GPUs and both GPUs are usable. Fairly significant power saving can be achieved by defaulting to the integrated graphics when high performance is not required. In total there are 3 display outputs from the integrated graphics and an additional 6 outputs from the Radeon graphics for a total of 9. |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |