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== Sockets/Platform == | == Sockets/Platform == | ||
− | {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2-die [[multi-chip package]] (MCP) whereas the {{intel|Kaby Lake U|l=core}}'s are either 2 or 3-die MCP configuration. The 3 | + | {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2-die [[multi-chip package]] (MCP) whereas the {{intel|Kaby Lake U|l=core}}'s are either 2 or 3-die MCP configuration. The 3 dice chip configuration are for the Iris [[IGP]]s which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|H|l=core}} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only {{intel|Kaby Lake S|l=core}} (used on mainstream desktop processors) are not soldered onto the [[motherboard]] and can be interchanged/replaced. |
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Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |