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Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the modified process "14nm+". The new process has improved [[transistor]] channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 [[megahertz]] which gives many [[single-thread]] applications a modest performance increase. Overall transistors improvement allowed for +12% drive current. | Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the modified process "14nm+". The new process has improved [[transistor]] channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 [[megahertz]] which gives many [[single-thread]] applications a modest performance increase. Overall transistors improvement allowed for +12% drive current. | ||
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |