Revision as of 19:57, 29 March 2017

Ivy Bridge (IVB) was Intel's microarchitecture based on the 22 nm process for desktops and servers. Ivy Bridge was introduced in 2011 as a process shrink of Sandy Bridge which introduced a number enhancements. Ivy Bridge became Intel's first microarchitecture to use tri-gate transistors for their commercial products.

For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel Core processors. For server class processors, Intel branded it as Xeon E3 v2, Xeon E5 v2, and Xeon E7 v2.

Codenames

This section is empty; you can help add the missing info by editing this page.

Process Technology

Ivy Bridge is designed to be manufactured using 22 nm Tri-gate FinFET transistors. This is Intel's first generation of FinFET. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively.

Scaling:

	Sandy Bridge	Ivy Bridge	Δ
	32 nm	22 nm
Fin Pitch	N/A	60 nm	N/A
Fin Width​		8 nm
Fin Height​		34 nm
Gate Pitch	112.5 nm	90 nm	0.80x
Interconnect Pitch	112.5 nm	80 nm	0.71x

Architecture

This section is empty; you can help add the missing info by editing this page.

Die

Hexa-core Ivy Bridge Die

• Core i7-4960X
• 1,860,000,000 transistors
• 256.5 mm²
• 15.0 mm x 17.1 mm

Quad-core Ivy Bridge die

• 1,480,000,000 transistors
• 160 mm²
• 4 CPU cores
• 1 GPU core
  • 2x8xEU (64 ALUs)
• 22 nm process

Cores

This section is empty; you can help add the missing info by editing this page.

All Ivy Bridge Chips