From WikiChip
Difference between revisions of "intel/microarchitectures/ice lake (server)"
< intel‎ | microarchitectures

(New instructions)
Line 85: Line 85:
 
** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} -  AVX-512 Vector Vector Carry-less Multiply
 
** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} -  AVX-512 Vector Vector Carry-less Multiply
 
* {{x86|TME|<code>TME</code>}} - Total Memory Encryption
 
* {{x86|TME|<code>TME</code>}} - Total Memory Encryption
 +
* {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
 
* Fast Short REP MOV
 
* Fast Short REP MOV
 +
* Split Lock Detection
  
 
== All Ice Lake Chips ==
 
== All Ice Lake Chips ==

Revision as of 14:10, 4 April 2018

Edit Values
Ice Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesIce Lake SP,
Ice Lake X
Succession
Contemporary
Ice Lake (client)

Ice Lake (ICL) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.

Codenames

Core Abbrev Target
Ice Lake X ICL-X High-end desktops & enthusiasts market
Ice Lake W ICL-W Enterprise/Business workstations
Ice Lake SP ICL-SP Server Scalable Processors

Process Technology

See also: Ice Lake (client) § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake -mtune=icelake
GCC -march=icelake -mtune=icelake
LLVM -march=icelake -mtune=icelake
Visual Studio /? /tune:?

CPUID

Core Extended
Family
Family Extended
Model
Model
 ? 0 0x6 0x?  ?
Family 6 Model ?
 ? 0 0x6  ?  ?
Family 6 Model ?

Architecture

Not much is known about Ice Lake's architecture.

Key changes from Cascade Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Enhanced "10nm+" (from 14 nm)

New instructions

Ice Lake introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • RDPID - Read Processor ID
  • Additional AVX-512 extensions:
  • TME - Total Memory Encryption
  • ENCLV - SGX oversubscription instructions
  • Fast Short REP MOV
  • Split Lock Detection

All Ice Lake Chips

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake Processors
 Main processorFrequency/TurboMemMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequencyMax TurboMax MemTurboSMT
 Uniprocessors
 Multiprocessors (2-way)
 Multiprocessors (4-way)
 Multiprocessors (8-way)
Count: 0
codenameIce Lake +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake +
process10 nm (0.01 μm, 1.0e-5 mm) +