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Latest revision | Your text | ||
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====New instructions ==== | ====New instructions ==== | ||
− | Ice Lake introduced a number of {{x86|extensions|new instructions}} | + | Ice Lake introduced a number of {{x86|extensions|new instructions}}: |
+ | |||
+ | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
+ | * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID | ||
+ | * Additional {{x86|AVX-512}} extensions: | ||
+ | ** {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword | ||
+ | ** {{x86|AVX512VNNI|<code>AVX512VNNI</code>}} - AVX-512 Vector Neural Network Instructions | ||
+ | ** {{x86|AVX512GFNI|<code>AVX512GFNI</code>}} - AVX-512 Galois Field New Instructions | ||
+ | ** {{x86|AVX512VAES|<code>AVX512VAES</code>}} - AVX-512 Vector AES | ||
+ | ** {{x86|AVX512VBMI2|<code>AVX512VBMI2</code>}} - AVX-512 Vector Bit Manipulation, Version 2 | ||
+ | ** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} - AVX-512 Bit Algorithms | ||
+ | ** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} - AVX-512 Vector Vector Carry-less Multiply | ||
+ | * {{x86|TME|<code>TME</code>}} - Total Memory Encryption | ||
+ | * {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions | ||
+ | * Fast Short REP MOV | ||
+ | * Split Lock Detection | ||
== All Ice Lake Chips == | == All Ice Lake Chips == |
Facts about "Ice Lake (server) - Microarchitectures - Intel"
codename | Ice Lake (server) + |
core count | 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | April 2021 + |
full page name | intel/microarchitectures/ice lake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |