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Ice Lake (client) - Microarchitectures - Intel
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Ice Lake (client) µarch
General Info
Arch TypeCPU
Process10 nm
L1I Cache32 KiB/core
8-way set associative
L1D Cache48 KiB/core
12-way set associative
L2 Cache512 KiB/512 KiB
12-way set associative
L3 Cache2 MiB/core
16-way set associative
Core NamesIce Lake Y,
Ice Lake U
Ice Lake (server)

Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.


Core Abbrev Description Graphics Target
Ice Lake Y ICL-Y Extremely low power 2-in-1s detachable, tablets, and computer sticks
Ice Lake U ICL-U Ultra-low Power Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Ice Lake H ICL-H High-performance Graphics Ultimate mobile performance, mobile workstations
Ice Lake S? ICL-S Performance-optimized lifestyle Desktop performance to value, AiOs, and minis

Process Technology

See also: Cannon Lake § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

intels 10+ and 10++.png

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake -mtune=icelake
GCC -march=icelake -mtune=icelake
LLVM -march=icelake -mtune=icelake
Visual Studio /? /tune:?


Core Extended
Family Extended
U, Y 0 0x6 0x7 0xE
Family 6 Model 126
 ? 0 0x6  ?  ?
Family 6 Model ?


Not much is known about Ice Lake's architecture.

Key changes from Cannon Lake

  • Enhanced "10nm+" (from "10nm", 2nd gen)
  • Sunny Cove core (from Palm Cove)
    • See Sunny Cove for microarchitectural details and changes
  • Gen10Gen11 graphics
  • Gen11 GPUs
    • UHD Graphics 7xx (GT1) UHD Graphics 8xx (GT1) (32 Execution Units, 1.3x EUs from Cannon Lake)
    • UHD Graphics 7xx (GT2) UHD Graphics 8xx (Gt2) (64 Execution Units, 1.6x EUs from Cannon Lake)
  • Display
    • DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
    • HDMI 2.0 (from HDMI 1.4)

This list is incomplete; you can help by expanding it.

New instructions

Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.

Block Diagram

Entire SoC Overview

ice lake soc block diagram.svg

Individual Core

See Sunny Cove § Block Diagram.

Gen11 Graphics

See Gen11 Graphics § Block Diagram.

All Ice Lake Chips

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake-based Processors
 Main processorTurbo BoostMemoryGPUFeatures
ModelLaunchedPriceFamilyPlatformCoreCoresThreadsL3$TDPBase1 Core2 Cores4 Cores6 CoresMax MemoryNameBaseBurstTBTHT
Count: 0
codenameIce Lake (client) +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/ice lake (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (client) +
process10 nm (0.01 μm, 1.0e-5 mm) +