From WikiChip
Editing intel/microarchitectures/ice lake (client)

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 202: Line 202:
 
The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC that is aimed at the mainstream to premium mobile and the thin-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance.
 
The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC that is aimed at the mainstream to premium mobile and the thin-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance.
  
The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). Ice Lake integrates the entire Thunderbolt 3 I/O subsystem on-die, significantly simplifying support at the system level. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression.
+
The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). There is a new Thunderbolt 3 integration. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression.
  
 
Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH  The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}.
 
Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH  The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}.

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

This page is a member of 1 hidden category:

codenameIce Lake (client) +
core count2 + and 4 +
designerIntel +
first launchedMay 27, 2019 +
full page nameintel/microarchitectures/ice lake (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (client) +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +