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== Overview ==
 
== Overview ==
 
[[File:ice lake overview.svg|right|500px]]
 
[[File:ice lake overview.svg|right|500px]]
The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC that is aimed at the mainstream to premium mobile and the thin-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance.
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The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC aimed at mainstream to premium mobile and thin & light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance.
  
 
The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). Ice Lake integrates the entire Thunderbolt 3 I/O subsystem on-die, significantly simplifying support at the system level. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression.
 
The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). Ice Lake integrates the entire Thunderbolt 3 I/O subsystem on-die, significantly simplifying support at the system level. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression.

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codenameIce Lake (client) +
core count2 + and 4 +
designerIntel +
first launchedMay 27, 2019 +
full page nameintel/microarchitectures/ice lake (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (client) +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +