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=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With Haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.
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The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.
  
 
* Cache
 
* Cache
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=== Server Die ===
 
=== Server Die ===
  
====Octadeca-core====
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====Octadaca-core====
 
* [[18 cores]] processor
 
* [[18 cores]] processor
 
* [[22 nm process]]
 
* [[22 nm process]]

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codenameHaswell +
core count2 +, 4 +, 6 +, 8 + and 16 +
designerIntel +
first launchedJune 4, 2013 +
full page nameintel/microarchitectures/haswell (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameHaswell +
phase-out2015 +
pipeline stages (max)19 +
pipeline stages (min)14 +
process22 nm (0.022 μm, 2.2e-5 mm) +