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==== CPU changes ====
 
==== CPU changes ====
Haswell can do many general purpose instructions with 4 ops/cycle throughput. SandyBridge/Ivybridge could do so only for NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs).
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Haswell can execute more classes of instructions with 4 ops/cycle throughput. SandyBridge/Ivybridge could do so only for NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs).
 
* MOVSX and MOVZX have 4 op/cycle throughput for 8->32, 8->64 and 16->64 bit forms.
 
* MOVSX and MOVZX have 4 op/cycle throughput for 8->32, 8->64 and 16->64 bit forms.
* Many ALU operations have 4 op/cycle throughput for GP registers: XOR, OR, NEG, NOT, ADD, SUB, CMP, AND, etc.
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* Some ALU operations have 4 op/cycle throughput for 32-bit registers: XOR, OR, NEG, NOT, although not all (ADD, SUB, CMP and AND don't).
 
* Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles, variable SHLD/SHRD from 2 cycles to 4 cycles.
 
* Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles, variable SHLD/SHRD from 2 cycles to 4 cycles.
 
* REP MOVS copy is twice as fast: now ~52 bytes/cycle.
 
* REP MOVS copy is twice as fast: now ~52 bytes/cycle.
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=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With Haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.
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The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.
  
 
* Cache
 
* Cache
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==== Front-end ====
 
==== Front-end ====
The front-end is the complicated part of the microarchitecture as it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public.
+
The front-end is the complicated part of the microarchitecture has it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public.
  
 
Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads.
 
Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads.
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{{oc warning}}
 
{{oc warning}}
  
Overclocking needs to be done on an unlocked part such as the [[Core i7-5820K]], [[Core i7-5930K]], or [[Core i7-5960X]] Extreme Edition. Additionally those chips need to be paired with the Intel X99 Chipset.
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Overclocking needs to be done on an unlocked part such as the [[Core i7-5820K]], [[Core i7-5930K]], or [[Core i7-5960X]] Extreme Edition. Additionally those chips needs to be paired with the Intel X99 Chipset.
  
 
[[File:haswell oc chips.png|500px|left]]
 
[[File:haswell oc chips.png|500px|left]]
  
The 5930K and the 5820K are [[hexa-core]] parts whereas the [[5960X]] is an octa-core part. Between 28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]].
+
The 5930K and the 5820K are [[hex-core]] parts whereas the [[5960X]] is an octa-core part. Between 28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]].
  
 
[[File:haswell bclk.png|300px|right]]
 
[[File:haswell bclk.png|300px|right]]
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Client die come in [[dual-core|2]], [[quad-core|4]], or [[octa-core|8]] cores setup with dual/quad being mainstream models and the [[octa-core]] being the high-end desktop.
 
Client die come in [[dual-core|2]], [[quad-core|4]], or [[octa-core|8]] cores setup with dual/quad being mainstream models and the [[octa-core]] being the high-end desktop.
  
==== Dual-core GT2 ====
+
====Dual-core ====
* 22 nm process
 
* 960,000,000 transistors
 
* 131 mm² die size
 
* 2 CPU cores
 
  
==== Dual-core GT3 ====
+
: [[File:haswell die (dual-core).jpg|850px]]
* 22 nm process
 
* 1,300,000,000 transistors
 
* 181 mm² die size
 
* 2 CPU cores
 
  
: [[File:haswell gt3 die (dual-core).jpg|850px]]
+
====Quad-core ====
 
 
====Quad-core GT2 ====
 
 
* [[22 nm process]]
 
* [[22 nm process]]
 
* 1,400,000,000 transistors
 
* 1,400,000,000 transistors
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: [[File:haswell die (quad-core) (annotated).png|850px]]
 
: [[File:haswell die (quad-core) (annotated).png|850px]]
 
====Quad-core GT3 ====
 
* [[22 nm process]]
 
* 1,700,000,000 transistors
 
* 260 mm² die size
 
* 4 CPU cores
 
  
 
====Octa-core ====
 
====Octa-core ====
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=== Server Die ===
 
=== Server Die ===
  
====Octadeca-core====
+
====Octadaca-core====
 
* [[18 cores]] processor
 
* [[18 cores]] processor
 
* [[22 nm process]]
 
* [[22 nm process]]
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
 
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
 
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Uniprocessors]]</th></tr>
 
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::1]]
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::1]]
|?full page name
 
|?model number
 
|?first launched
 
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|?l3$ size
 
|?tdp
 
|?base frequency#GHz
 
|?turbo frequency (1 core)#GHz
 
|?turbo frequency (2 cores)#GHz
 
|?turbo frequency (3 cores)#GHz
 
|?turbo frequency (4 cores)#GHz
 
|?max memory#GiB
 
|?integrated gpu
 
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|format=template
 
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|searchlabel=
 
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<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Multiprocessors]] (2-way)</th></tr>
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::2]]
 
|?full page name
 
|?model number
 
|?first launched
 
|?release price
 
|?microprocessor family
 
|?core name
 
|?core count
 
|?thread count
 
|?l2$ size
 
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|?tdp
 
|?base frequency#GHz
 
|?turbo frequency (1 core)#GHz
 
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<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Multiprocessors]] (4-way)</th></tr>
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::4]]
 
|?full page name
 
|?model number
 
|?first launched
 
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|?microprocessor family
 
|?core name
 
|?core count
 
|?thread count
 
|?l2$ size
 
|?l3$ size
 
|?tdp
 
|?base frequency#GHz
 
|?turbo frequency (1 core)#GHz
 
|?turbo frequency (2 cores)#GHz
 
|?turbo frequency (3 cores)#GHz
 
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<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Multiprocessors]] (8-way)</th></tr>
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::8]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number

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codenameHaswell +
core count2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 +
designerIntel +
first launchedJune 4, 2013 +
full page nameintel/microarchitectures/haswell (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameHaswell +
phase-out2015 +
pipeline stages (max)19 +
pipeline stages (min)14 +
process22 nm (0.022 μm, 2.2e-5 mm) +