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Difference between revisions of "intel/microarchitectures/gracemont"
< intel‎ | microarchitectures

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{{intel title|Gracemont|arch}}
+
S
{{microarchitecture
 
|atype=CPU
 
|name=Gracemont
 
|designer=Intel
 
|manufacturer=Intel
 
|introduction=2021
 
|process=10 nm
 
|type=Superscalar
 
|oooe=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|isa=x86-64
 
|extension=MOVBE
 
|extension 2=MMX
 
|extension 3=SSE
 
|extension 4=SSE2
 
|extension 5=SSE3
 
|extension 6=SSSE3
 
|extension 7=SSE4.1
 
|extension 8=SSE4.2
 
|extension 9=POPCNT
 
|extension 10=AES
 
|extension 11=PCLMUL
 
|extension 12=RDRND
 
|extension 13=XSAVE
 
|extension 14=XSAVEOPT
 
|extension 15=FSGSBASE
 
|extension 16=PTWRITE
 
|extension 17=RDPID
 
|extension 18=SGX
 
|extension 19=UMIP
 
|extension 20=GFNI-SSE
 
|extension 21=CLWB
 
|extension 22=ENCLV
 
|extension 23=SHA
 
|core name=
 
|core name 2=
 
|core name 3=
 
|predecessor=Tremont
 
|predecessor link=intel/microarchitectures/tremont
 
}}
 
'''Gracemont''' is [[Intel]]'s successor to {{\\|Tremont}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.
 
 
 
== Process Technology ==
 
Gracemont is designed to take advantage of Intel's [[10 nm process]].
 
 
 
== Architecture ==
 
=== Key changes from {{\\|Tremont}}===
 
{{future information}}
 

Revision as of 18:47, 23 March 2020

S

codenameGracemont +
designerIntel +
first launched2021 +
full page nameintel/microarchitectures/gracemont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGracemont +
process10 nm (0.01 μm, 1.0e-5 mm) +