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Difference between revisions of "intel/microarchitectures/gracemont"
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* Core
 
* Core
 
** Larger Level 1 instruction cache - 64KB per core from 32KB per core
 
** Larger Level 1 instruction cache - 64KB per core from 32KB per core
 +
** IPC increase to Skylake-level
 
* Memory
 
* Memory
 
** DDR5 (from DDR4)
 
** DDR5 (from DDR4)
 
* I/O
 
* I/O
 
** PCIe 4.0 (from 3.0)
 
** PCIe 4.0 (from 3.0)

Revision as of 14:37, 25 April 2021

Edit Values
Gracemont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2021
Process10 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA
Succession

Gracemont is Intel's successor to Tremont, a 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames

Platform Core Name PCH
Grand Ridge

Process Technology

Gracemont is designed to take advantage of Intel's 10 nm process.

Architecture

Key changes from Tremont

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Core
    • Larger Level 1 instruction cache - 64KB per core from 32KB per core
    • IPC increase to Skylake-level
  • Memory
    • DDR5 (from DDR4)
  • I/O
    • PCIe 4.0 (from 3.0)
codenameGracemont +
designerIntel +
first launched2021 +
full page nameintel/microarchitectures/gracemont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGracemont +
process10 nm (0.01 μm, 1.0e-5 mm) +