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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Global Attributes''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Global Attributes''' |
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− | |Slice count || 1 || 1 || 1 || 2
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− | |-
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− | |Subslice Count || 2 || 3 || 3 || 6
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− | |-
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− | |EU/Subslice || 6 || 6 || 8 || 8
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− | |-
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− | |EU count (total) || 12 || 18 || 24 || 48
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− | |-
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− | |Thread Count || 7 || 7 || 7 || 7
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− | |-
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− | |Thread Count (Total) || 84 || 126 || 161 / 168 || 329 / 336
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− | |FLOPs/Clk - Half Precision, MAD (peak) || 384 || 576 || 736 / 768 || 1504 / 1536
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− | |-
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− | |FLOPs/Clk - Single Precision, MAD (peak) || 192 || 288 || 368 / 384 || 752 / 768
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− | |-
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− | |FLOPs/Clk - Double Precision, MAD (peak) || 48 || 72 || 92 / 96 || 188 / 192
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− | |-
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− | |Unslice clocking (coupled/decoupled from Cr slice) || coupled || coupled || coupled || coupled
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− | |GTI / Ring Interfaces || 1 || 1 || 1 || 1
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− | |GTI bandwidth (bytes/unslice-clk) || 64: R<br>64: W || 64: R<br>64: W || 64: R<br>64: W || 64: R<br>64: W
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− | |-
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− | |eDRAM Support || N/A || N/A || N/A || 0, 64 MiB
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− | |Graphics Virtual Address Range || 48 bit || 48 bit || 48 bit || 48 bit
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− | |-
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− | |Graphics Physical Address Range || 39 bit || 39 bit || 39 bit || 39 bit
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Caches & Dedicated Memories''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Caches & Dedicated Memories''' |
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− | |L3 Cache, total size (bytes) || 384K || 768K || 768K || 1536K
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− | |L3 Cache, bank count || 2 || 4 || 4 || 8
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− | |L3 Cache, bandwidth (bytes/clk) || 2x 64: R 2x 64: W || 4x 64: R 4x 64: W || 4x 64: R 4x 64: W || 8x 64: R 8x 64: W
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− | |L3 Cache, D$ Size (Kbytes) || 192K - 256K || 512K || 512K || 1024K
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− | |URB Size (kbytes) || 128K - 192K || 384K || 384K || 768K
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− | |SLM Size (kbytes) || 0, 128K || 0, 192K || 0, 192K || 0, 384K
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− | |LLC/L4 size (bytes) || ~2MiB/CPU core || ~2MiB/CPU core || ~2MiB/CPU core || ~2MiB/CPU core
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− | |Instruction Cache (IC, bytes) || 2x 48K || 3x 48K || 3x 48K || 6x 48K
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− | |Color Cache (RCC, bytes) || 24K || 24K || 24K || 2x 24K
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− | |-
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− | |MSC Cache (MSC, bytes) || 16K || 16K || 16K || 2x 16K
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− | |-
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− | |HiZ Cache (HZC, bytes) || 12K || 12K || 12K || 2x 12K
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− | |-
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− | |Z Cache (RCZ, bytes) || 32K || 32K || 32K || 2x 32K
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− | |-
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− | |Stencil Cache (STC, bytes) || 8K || 8K || 8K || 2x 8K
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Instruction Issue Rates''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Instruction Issue Rates''' |
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− | |FMAD, SP (ops/EU/clk) || 8 || 8 || 8 || 8
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− | |FMUL, SP (ops/EU/clk) || 8 || 8 || 8 || 8
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− | |-
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− | |FADD, SP (ops/EU/clk) || 8 || 8 || 8 || 8
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− | |-
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− | |MIN,MAX, SP (ops/EU/clk) || 8 || 8 || 8 || 8
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− | |-
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− | |CMP, SP (ops/EU/clk) || 8 || 8 || 8 || 8
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− | |-
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− | |INV, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |-
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− | |SQRT, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |RSQRT, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |LOG, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |-
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− | |EXP, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |-
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− | |POW, SP (ops/EU/clk) || 1 || 1 || 1 || 1
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− | |IDIV, SP (ops/EU/clk) || 1-6 || 1-6 || 1-6 || 1-6
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− | |TRIG, SP (ops/EU/clk) || 2 || 2 || 2 || 2
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− | |-
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− | |FDIV, SP (ops/EU/clk) || 1 || 1 || 1 || 1
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Load/Store''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Load/Store''' |
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− | |Data Ports (HDC) || 2 || 3 || 3 || 6
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− | |L3 Load/Store (dwords/clk) || 2x 64 || 3x 64 || 3x 64 || 6x 64
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− | |SLM Load/Store (dwords/clk) || 2x 64 || 3x 64 || 3x 64 || 6x 64
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− | |Atomic Inc, 32b - sequential addresses (dwords/clk) || 2x 64 || 3x 64 || 3x 64 || 6x 64
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− | |Atomic Inc, 32b - same address (dwords/clk) || 2x 4 || 3x 4 || 3x 4 || 6x 4
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− | |-
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− | |Atomic CmpWr, 32b - sequential addresses (dwords/clk) || 2x 32 || 3x 32 || 3x 32 || 6x 32
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− | |-
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− | |Atomic CmpWr, 32b - same address (dwords/clk) || 2x 4 || 3x 4 || 3x 4 || 6x 4
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''3D Attributes''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''3D Attributes''' |
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− | |Geometry pipes || 1 || 1 || 1 || 1
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− | |Samplers (3D) || 2 || 3 || 3 || 6
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− | |Texel Rate, point, 32b (tex/clk) || 8 || 12 || 12 || 24
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− | |-
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− | |Texel Rate, point, 64b (tex/clk) || 8 || 12 || 12 || 24
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− | |Texel Rate, point, 128b (tex/clk) || 8 || 12 || 12 || 24
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− | |Texel Rate, bilinear, 32b (tex/clk) || 8 || 12 || 12 || 24
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− | |Texel Rate, bilinear, 64b (tex/clk) || 8 || 12 || 12 || 24
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− | |Texel Rate, bilinear, 128b (tex/clk) || 2 || 3 || 3 || 6
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− | |Texel Rate, trilinear, 32b (tex/clk) || 8 || 12 || 12 || 24
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− | |Texel Rate, trilinear, 64b (tex/clk) || 4 || 6 || 6 || 12
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− | |Texel Rate, trilinear, 128b (tex/clk) || 1 || 1.5 || 1.5 || 3
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− | |Texel Rate, aniso 2x, MIP Linear,, 32b (tex/clk) || 2 || 3 || 3 || 6
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− | |Texel Rate, aniso 4x, MIP Linear,, 32b (tex/clk) || 1 || 1.5 || 1.5 || 3
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− | |Texel Rate, ansio 8x, MIP Linear,, 32b (tex/clk) || 0.5 || 0.75 || 0.75 || 1.5
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− | |Texel Rate, ansio 16x, MIP Linear,, 32b (tex/clk) || 0.25 || 0.375 || 0.375 || 0.75
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− | |-
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− | |HiZ Rate, (ppc) || 64 || 64 || 64 || 2x 64
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− | |-
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− | |IZ Rate, (ppc) || 16 || 16 || 16 || 2x 16
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− | |-
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− | |Stencil Rate (ppc) || 64 || 64 || 64 || 2x 64
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Media Attributes''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Media Attributes''' |
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− | |Samplers (media) || 2 || 3 || 3 || 6
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− | |-
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− | |VDBox Instances || 1 || 1 || 1 || 2
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− | |-
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− | |VEBox Instances || 1 || 1 || 1 || 2
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− | |-
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− | |SFC Instances || 1 || 1 || 1 || 1
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| | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Display Attributes''' | | | colspan="7" style="background:#f2f7ff; text-align: center;" | '''Display Attributes''' |
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− | |Display Pipes || 3 || 3 || 3 || 3
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− | |-
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− | |Display Planes per Pipe || 3 || 3 || 3 || 3
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− | |-
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− | |DDI ports || 2 || 2 || 2 || 2
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− | |-
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− | |eDP ports || 1 || 1 || 1 || 1
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| |} | | |} |