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{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
 
|-
 
|-
! colspan="5" | Gen9 [[IGP]] Models !! colspan="10" | Standards
+
! colspan="5" | Gen9 [[IGP]] Models !! colspan="9" | Standards
 
|-
 
|-
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] !! colspan="1" | [[Metal]]
+
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
 
|-
 
|-
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux || macOS
+
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" colspan="2" | '''2.0''' || rowspan="8" style="text-align: center;" colspan="1" | '''2.1'''
+
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" colspan="2" | '''2.0'''
 
|-
 
|-
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
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| Ref (FLOP/clk) || 384/cycle || 768/cycle || 1536/cycle || 2304/cycle || 192/cycle || 384/cycle || 768/cycle || 1152/cycle || 48/cycle || 96/cycle || 192/cycle || 288/cycle
 
| Ref (FLOP/clk) || 384/cycle || 768/cycle || 1536/cycle || 2304/cycle || 192/cycle || 384/cycle || 768/cycle || 1152/cycle || 48/cycle || 96/cycle || 192/cycle || 288/cycle
 
|-
 
|-
| Base (300 MHz) || {{#expr: 384*.3}} [[GFLOPS]] || {{#expr: 768*.3}} GFLOPS || {{#expr: 1536*.3}} GFLOPS || {{#expr: 2304*.3}} GFLOPS || {{#expr: 192*.3}} GFLOPS || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 1152*.3}} GFLOPS || {{#expr: 48*.3}} GFLOPS || {{#expr: 96*.3}} GFLOPS || {{#expr: 129*.3}} GFLOPS || {{#expr: 288*.3}} GFLOPS
+
| Base (300 MHz) || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 1536*.3}} GFLOPS || {{#expr: 2304*.3}} GFLOPS || {{#expr: 192*.3}} GFLOPS || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 1152*.3}} GFLOPS || {{#expr: 48*.3}} GFLOPS || {{#expr: 96*.3}} GFLOPS || {{#expr: 129*.3}} GFLOPS || {{#expr: 288*.3}} GFLOPS
 
|-
 
|-
 
| Base (350 MHz) || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1536*.35}} GFLOPS || {{#expr: 2304*.35}} GFLOPS || {{#expr: 192*.35}} GFLOPS || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1152*.35}} GFLOPS || {{#expr: 48*.35}} GFLOPS || {{#expr: 96*.35}} GFLOPS || {{#expr: 129*.35}} GFLOPS || {{#expr: 288*.35}} GFLOPS
 
| Base (350 MHz) || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1536*.35}} GFLOPS || {{#expr: 2304*.35}} GFLOPS || {{#expr: 192*.35}} GFLOPS || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1152*.35}} GFLOPS || {{#expr: 48*.35}} GFLOPS || {{#expr: 96*.35}} GFLOPS || {{#expr: 129*.35}} GFLOPS || {{#expr: 288*.35}} GFLOPS
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=== Key changes from {{\\|Gen8}} ===
 
=== Key changes from {{\\|Gen8}} ===
 
* Architecture is drastically different
 
* Architecture is drastically different
** Gen9 is composed of 3 truly independent major components: Display block, Unslice, and the Slice.
+
** Gen9 is composed of 3 truely independent major components: Display block, Unslice, and the Slice.
 
** Shared Virtual Memory (SVM) improvements
 
** Shared Virtual Memory (SVM) improvements
 
*** Improved cache coherency performance
 
*** Improved cache coherency performance
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=== Display ===
 
=== Display ===
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/270 rotations.
+
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/207 rotations.
 
   
 
   
 
[[File:gen9 display block.svg|650px]]
 
[[File:gen9 display block.svg|650px]]

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codenameGen9 +
designerIntel +
first launchedAugust 5, 2015 +
full page nameintel/microarchitectures/gen9 +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeGPU +
nameGen9 +
process14 nm (0.014 μm, 1.4e-5 mm) +