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{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
 
|-
 
|-
! colspan="5" | Gen9 [[IGP]] Models !! colspan="10" | Standards
+
! colspan="5" | Gen9 [[IGP]] Models !! colspan="9" | Standards
 
|-
 
|-
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] !! colspan="1" | [[Metal]]
+
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
 
|-
 
|-
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux || macOS
+
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" colspan="2" | '''2.0''' || rowspan="8" style="text-align: center;" colspan="1" | '''2.1'''
+
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="9" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="9" style="text-align: center;" | '''12''' || rowspan="9" style="text-align: center;" | '''N/A''' || rowspan="9" style="text-align: center;" | '''5.1''' || rowspan="9" style="text-align: center;" | '''4.4''' || rowspan="9" style="text-align: center;" | '''4.5''' || rowspan="9" style="text-align: center;" colspan="2" | '''2.0'''
 
|-
 
|-
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
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|-
 
|-
 
| {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB
 
| {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB
|-
 
| {{intel|Iris Pro Graphics P555}} || 48 || GT3e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
 
|-
 
|-
 
| {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
| {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
|-
 
| {{intel|Iris Pro Graphics P580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
 
|}
 
|}
  
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| {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA
 
| {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA
 
|-
 
|-
| {{intel|Iris Pro Graphics P555}} || SKL Media Server 4+3FE || N0 || J0 || 0x192D || 0x9
+
| {{intel|Iris Graphics P555}} || SKL Media Server 4+3FE || N0 || J0 || 0x192D || 0x9
 
|-
 
|-
| {{intel|Iris Pro Graphics 580}} || SKL H Halo 4+4E || rowspan="2" | 72 || N0 || J0 || 0x193B || 0x9
+
| rowspan="2" | {{intel|Iris Pro Graphics P580}} || SKL H Halo 4+4E || rowspan="2" | 72 || N0 || J0 || 0x193B || 0x9
 
|-
 
|-
| {{intel|Iris Pro Graphics P580}}  || SKL WKS 4+4E || N0 || J0 || 0x193D || 0x9
+
| SKL WKS 4+4E || N0 || J0 || 0x193D || 0x9
 
|}
 
|}
  
 
<references group=devID />
 
<references group=devID />
 
== Performance ==
 
<div style="overflow-x: auto;">
 
{| class="wikitable" style="text-align: center; white-space: nowrap;"
 
! rowspan="2" | Frequency !! colspan="15" | Peak Performance
 
|-
 
! rowspan="16" | &nbsp; || colspan="4" | Half Precision || rowspan="16" | &nbsp; || colspan="4" | Single Precision || rowspan="16" | &nbsp; || colspan="4" | Double Precision
 
|-
 
| Models || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}} || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}} || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}}
 
|-
 
| Tiers || GT1 || GT2 || GT3e || GT4e || GT1 || GT2 || GT3e || GT4e ||  GT1 || GT2 || GT3e || GT4e
 
|-
 
| Ref (FLOP/clk) || 384/cycle || 768/cycle || 1536/cycle || 2304/cycle || 192/cycle || 384/cycle || 768/cycle || 1152/cycle || 48/cycle || 96/cycle || 192/cycle || 288/cycle
 
|-
 
| Base (300 MHz) || {{#expr: 384*.3}} [[GFLOPS]] || {{#expr: 768*.3}} GFLOPS || {{#expr: 1536*.3}} GFLOPS || {{#expr: 2304*.3}} GFLOPS || {{#expr: 192*.3}} GFLOPS || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 1152*.3}} GFLOPS || {{#expr: 48*.3}} GFLOPS || {{#expr: 96*.3}} GFLOPS || {{#expr: 129*.3}} GFLOPS || {{#expr: 288*.3}} GFLOPS
 
|-
 
| Base (350 MHz) || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1536*.35}} GFLOPS || {{#expr: 2304*.35}} GFLOPS || {{#expr: 192*.35}} GFLOPS || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1152*.35}} GFLOPS || {{#expr: 48*.35}} GFLOPS || {{#expr: 96*.35}} GFLOPS || {{#expr: 129*.35}} GFLOPS || {{#expr: 288*.35}} GFLOPS
 
|-
 
| Base (400 MHz) || {{#expr: 384*.4}} GFLOPS || {{#expr: 768*.4}} GFLOPS || {{#expr: 1536*.4}} GFLOPS || {{#expr: 2304*.4}} GFLOPS || {{#expr: 192*.4}} GFLOPS || {{#expr: 384*.4}} GFLOPS || {{#expr: 768*.4}} GFLOPS || {{#expr: 1152*.4}} GFLOPS || {{#expr: 48*.4}} GFLOPS || {{#expr: 96*.4}} GFLOPS || {{#expr: 129*.4}} GFLOPS || {{#expr: 288*.4}} GFLOPS
 
|-
 
| Base (650 MHz) || {{#expr: 384*.65}} GFLOPS || {{#expr: 768*.65}} GFLOPS || {{#expr: 1536*.65}} GFLOPS || {{#expr: 2304*.65}} GFLOPS || {{#expr: 192*.65}} GFLOPS || {{#expr: 384*.65}} GFLOPS || {{#expr: 768*.65}} GFLOPS || {{#expr: 1152*.65}} GFLOPS || {{#expr: 48*.65}} GFLOPS || {{#expr: 96*.65}} GFLOPS || {{#expr: 129*.65}} GFLOPS || {{#expr: 288*.65}} GFLOPS
 
|-
 
| Boost (800 MHz) || {{#expr: 384*.8}} GFLOPS || {{#expr: 768*.8}} GFLOPS || {{#expr: 1536*.8}} GFLOPS || {{#expr: 2304*.8}} GFLOPS || {{#expr: 192*.8}} GFLOPS || {{#expr: 384*.8}} GFLOPS || {{#expr: 768*.8}} GFLOPS || {{#expr: 1152*.8}} GFLOPS || {{#expr: 48*.8}} GFLOPS || {{#expr: 96*.8}} GFLOPS || {{#expr: 129*.8}} GFLOPS || {{#expr: 288*.8}} GFLOPS
 
|-
 
| Boost (850 MHz) || {{#expr: 384*.85}} GFLOPS || {{#expr: 768*.85}} GFLOPS || {{#expr: 1536*.85}} GFLOPS || {{#expr: 2304*.85}} GFLOPS || {{#expr: 192*.85}} GFLOPS || {{#expr: 384*.85}} GFLOPS || {{#expr: 768*.85}} GFLOPS || {{#expr: 1152*.85}} GFLOPS || {{#expr: 48*.85}} GFLOPS || {{#expr: 96*.85}} GFLOPS || {{#expr: 129*.85}} GFLOPS || {{#expr: 288*.85}} GFLOPS
 
|-
 
| Boost (900 MHz) || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{#expr: 1536*.9}} GFLOPS || {{#expr: 2304*.9}} GFLOPS || {{#expr: 192*.9}} GFLOPS || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{#expr: 1152*.9}} GFLOPS || {{#expr: 48*.9}} GFLOPS || {{#expr: 96*.9}} GFLOPS || {{#expr: 129*.9}} GFLOPS || {{#expr: 288*.9}} GFLOPS
 
|-
 
| Boost (950 MHz) || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{#expr: 1536*.95}} GFLOPS || {{#expr: 2304*.95}} GFLOPS || {{#expr: 192*.95}} GFLOPS || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{#expr: 1152*.95}} GFLOPS || {{#expr: 48*.95}} GFLOPS || {{#expr: 96*.95}} GFLOPS || {{#expr: 129*.95}} GFLOPS || {{#expr: 288*.95}} GFLOPS
 
|-
 
| Boost (1,000 MHz) || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{#expr: 1536*1}} GFLOPS || {{#expr: 2304*1}} GFLOPS || {{#expr: 192*1}} GFLOPS || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{#expr: 1152*1}} GFLOPS || {{#expr: 48*1}} GFLOPS || {{#expr: 96*1}} GFLOPS || {{#expr: 129*1}} GFLOPS || {{#expr: 288*1}} GFLOPS
 
|-
 
| Boost (1,050 MHz) || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{#expr: 1536*1.05}} GFLOPS || {{#expr: 2304*1.05}} GFLOPS || {{#expr: 192*1.05}} GFLOPS || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{#expr: 1152*1.05}} GFLOPS || {{#expr: 48*1.05}} GFLOPS || {{#expr: 96*1.05}} GFLOPS || {{#expr: 129*1.05}} GFLOPS || {{#expr: 288*1.05}} GFLOPS
 
|-
 
| Boost (1,100 MHz) || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{#expr: 1536*1.1}} GFLOPS || {{#expr: 2304*1.1}} GFLOPS || {{#expr: 192*1.1}} GFLOPS || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{#expr: 1152*1.1}} GFLOPS || {{#expr: 48*1.1}} GFLOPS || {{#expr: 96*1.1}} GFLOPS || {{#expr: 129*1.1}} GFLOPS || {{#expr: 288*1.1}} GFLOPS
 
|-
 
| Boost (1,150 MHz) || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{#expr: 1536*1.15}} GFLOPS || {{#expr: 2304*1.15}} GFLOPS || {{#expr: 192*1.15}} GFLOPS || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{#expr: 1152*1.15}} GFLOPS || {{#expr: 48*1.15}} GFLOPS || {{#expr: 96*1.15}} GFLOPS || {{#expr: 129*1.15}} GFLOPS || {{#expr: 288*1.15}} GFLOPS
 
|}
 
</div>
 
  
 
== Hardware Accelerated Video ==
 
== Hardware Accelerated Video ==
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=== Key changes from {{\\|Gen8}} ===
 
=== Key changes from {{\\|Gen8}} ===
 
* Architecture is drastically different
 
* Architecture is drastically different
** Gen9 is composed of 3 truly independent major components: Display block, Unslice, and the Slice.
+
** Gen9 is composed of 3 truely independent major components: Display block, Unslice, and the Slice.
 
** Shared Virtual Memory (SVM) improvements
 
** Shared Virtual Memory (SVM) improvements
 
*** Improved cache coherency performance
 
*** Improved cache coherency performance
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** RAW imaging capabilities
 
** RAW imaging capabilities
 
* Slice
 
* Slice
** Floating point atomics (min/max/cmpexch)
 
 
** L3 Cache
 
** L3 Cache
 
*** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice)
 
*** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice)
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** Multi-plane overlays
 
** Multi-plane overlays
 
** Texture samplers now natively support an NV12 YUV
 
** Texture samplers now natively support an NV12 YUV
** Min/max texture filtering
 
 
** Preemption of execution is now supported at the thread level
 
** Preemption of execution is now supported at the thread level
 
** Round robin scheduling of threads within an execution unit.
 
** Round robin scheduling of threads within an execution unit.
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=== Display ===
 
=== Display ===
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/270 rotations.
+
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/207 rotations.
 
   
 
   
 
[[File:gen9 display block.svg|650px]]
 
[[File:gen9 display block.svg|650px]]

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codenameGen9 +
designerIntel +
first launchedAugust 5, 2015 +
full page nameintel/microarchitectures/gen9 +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeGPU +
nameGen9 +
process14 nm (0.014 μm, 1.4e-5 mm) +