From WikiChip
Editing intel/microarchitectures/gen9
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 38: | Line 38: | ||
{| class="wikitable tc2 tc3" | {| class="wikitable tc2 tc3" | ||
|- | |- | ||
− | ! colspan="5" | Gen9 [[IGP]] Models !! colspan=" | + | ! colspan="5" | Gen9 [[IGP]] Models !! colspan="9" | Standards |
|- | |- | ||
− | ! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !! rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL | + | ! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !! rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] |
|- | |- | ||
− | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | + | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux |
|- | |- | ||
− | | {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan=" | + | | {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="9" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="9" style="text-align: center;" | '''12''' || rowspan="9" style="text-align: center;" | '''N/A''' || rowspan="9" style="text-align: center;" | '''5.1''' || rowspan="9" style="text-align: center;" | '''4.4''' || rowspan="9" style="text-align: center;" | '''4.5''' || rowspan="9" style="text-align: center;" colspan="2" | '''2.0''' |
|- | |- | ||
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || - | | {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || - | ||
Line 59: | Line 59: | ||
|- | |- | ||
| {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB | | {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB | ||
− | |||
− | |||
|- | |- | ||
| {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB | | {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB | ||
− | |||
− | |||
|} | |} | ||
Line 94: | Line 90: | ||
| {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA | | {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA | ||
|- | |- | ||
− | | {{intel|Iris | + | | {{intel|Iris Graphics P555}} || SKL Media Server 4+3FE || N0 || J0 || 0x192D || 0x9 |
|- | |- | ||
− | | {{intel|Iris Pro Graphics | + | | rowspan="2" | {{intel|Iris Pro Graphics P580}} || SKL H Halo 4+4E || rowspan="2" | 72 || N0 || J0 || 0x193B || 0x9 |
|- | |- | ||
− | + | | SKL WKS 4+4E || N0 || J0 || 0x193D || 0x9 | |
|} | |} | ||
<references group=devID /> | <references group=devID /> | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Hardware Accelerated Video == | == Hardware Accelerated Video == | ||
Line 154: | Line 111: | ||
=== Key changes from {{\\|Gen8}} === | === Key changes from {{\\|Gen8}} === | ||
* Architecture is drastically different | * Architecture is drastically different | ||
− | ** Gen9 is composed of 3 | + | ** Gen9 is composed of 3 truely independent major components: Display block, Unslice, and the Slice. |
** Shared Virtual Memory (SVM) improvements | ** Shared Virtual Memory (SVM) improvements | ||
*** Improved cache coherency performance | *** Improved cache coherency performance | ||
Line 167: | Line 124: | ||
** RAW imaging capabilities | ** RAW imaging capabilities | ||
* Slice | * Slice | ||
− | |||
** L3 Cache | ** L3 Cache | ||
*** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice) | *** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice) | ||
Line 177: | Line 133: | ||
** Multi-plane overlays | ** Multi-plane overlays | ||
** Texture samplers now natively support an NV12 YUV | ** Texture samplers now natively support an NV12 YUV | ||
− | |||
** Preemption of execution is now supported at the thread level | ** Preemption of execution is now supported at the thread level | ||
** Round robin scheduling of threads within an execution unit. | ** Round robin scheduling of threads within an execution unit. | ||
Line 277: | Line 232: | ||
=== Display === | === Display === | ||
− | The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/ | + | The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/207 rotations. |
[[File:gen9 display block.svg|650px]] | [[File:gen9 display block.svg|650px]] |
Facts about "Gen9 - Microarchitectures - Intel"
codename | Gen9 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/gen9 + |
instance of | microarchitecture + |
manufacturer | Intel + |
microarchitecture type | GPU + |
name | Gen9 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |