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{{intel title|Gen9|arch}}
+
{{intel title|Gen9 LP|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
| atype            = GPU
 
| atype            = GPU
| name            = Gen9
+
| name            = Gen9 LP
 
| designer        = Intel
 
| designer        = Intel
 
| manufacturer    = Intel
 
| manufacturer    = Intel
Line 10: Line 10:
  
 
| succession      = Yes
 
| succession      = Yes
| predecessor      = Gen8
+
| predecessor      = Gen8 LP
| predecessor link = intel/microarchitectures/gen8
+
| predecessor link = intel/microarchitectures/gen8_lp
| successor        = Gen9.5
+
| successor        = Gen9.5 LP
| successor link  = intel/microarchitectures/gen9.5
+
| successor link  = intel/microarchitectures/gen9.5_lp
 
}}
 
}}
'''Gen9''' (''Generation 9'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Skylake}}-based microprocessors. Gen9 is the successor to {{\\|Gen8}} used by {{\\|Broadwell}}. The Gen9 microarchitecture is designed separately by Intel and then integrated onto the same Skylake SoC die.
+
'''Gen9 LP''' (''Generation 9 Low Power'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Skylake}}-based microprocessors. Gen9 LP is the successor to {{\\|Gen8 LP}} used by {{\\|Broadwell}}. The Gen9 microarchitecture is designed separately by Intel and then integrated onto the same Skylake SoC die.
  
 
== Codenames ==
 
== Codenames ==
[[File:iris graphics logo.svg|right|200px]][[File:iris pro graphics logo.svg|right|200px]]
 
 
Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache.
 
Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache.
 
{| class="wikitable"
 
{| class="wikitable"
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{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
 
|-
 
|-
! colspan="5" | Gen9 [[IGP]] Models !! colspan="10" | Standards
+
! colspan="5" | Gen9 LP [[IGP]] Models !! colspan="9" | Standards
 
|-
 
|-
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] !! colspan="1" | [[Metal]]
+
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
 
|-
 
|-
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux || macOS
+
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" colspan="2" | '''2.0''' || rowspan="8" style="text-align: center;" colspan="1" | '''2.1'''
+
| {{intel|HD Graphics (Skylake)}} || 12 || GT1 || {{intel|Skylake Y|Y|l=core}} || - || rowspan="9" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="9" style="text-align: center;" | '''12''' || rowspan="9" style="text-align: center;" | '''N/A''' || rowspan="9" style="text-align: center;" | '''5.1''' || rowspan="9" style="text-align: center;" | '''4.4''' || rowspan="9" style="text-align: center;" | '''4.5''' || rowspan="9" style="text-align: center;" colspan="2" | '''2.0'''
 
|-
 
|-
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
 
| {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || -
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|-
 
|-
 
| {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB
 
| {{intel|Iris Graphics 550}} || 48 || GT3e || {{intel|Skylake U|U|l=core}} || 64 MiB
|-
 
| {{intel|Iris Pro Graphics P555}} || 48 || GT3e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
 
|-
 
|-
 
| {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
| {{intel|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
|-
 
| {{intel|Iris Pro Graphics P580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB
 
 
|}
 
|}
  
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| {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA
 
| {{intel|HD Graphics 535}} || SKL U - ULT 2+3 || K1 || L1 || 0x1923 || 0xA
 
|-
 
|-
| {{intel|Iris Pro Graphics P555}} || SKL Media Server 4+3FE || N0 || J0 || 0x192D || 0x9
+
| {{intel|Iris Graphics P555}} || SKL Media Server 4+3FE || N0 || J0 || 0x192D || 0x9
 
|-
 
|-
| {{intel|Iris Pro Graphics 580}} || SKL H Halo 4+4E || rowspan="2" | 72 || N0 || J0 || 0x193B || 0x9
+
| {{intel|Iris Pro Graphics P580}} || SKL H Halo 4+4E || rowspan="2" | 72 || N0 || J0 || 0x193B || 0x9
 
|-
 
|-
| {{intel|Iris Pro Graphics P580}} || SKL WKS 4+4E || N0 || J0 || 0x193D || 0x9
+
| {{intel|Iris Pro Graphics P580}} || SKL WKS 4+4E || N0 || J0 || 0x193D || 0x9
 
|}
 
|}
  
 
<references group=devID />
 
<references group=devID />
 
== Performance ==
 
<div style="overflow-x: auto;">
 
{| class="wikitable" style="text-align: center; white-space: nowrap;"
 
! rowspan="2" | Frequency !! colspan="15" | Peak Performance
 
|-
 
! rowspan="16" | &nbsp; || colspan="4" | Half Precision || rowspan="16" | &nbsp; || colspan="4" | Single Precision || rowspan="16" | &nbsp; || colspan="4" | Double Precision
 
|-
 
| Models || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}} || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}} || {{intel|HD Graphics 510|510}} || {{intel|HD Graphics 515|515}}, {{intel|HD Graphics 520|520}}, {{intel|HD Graphics 530|530}}, {{intel|HD Graphics P530|P530}} || {{intel|Iris Graphics 540|540}}, {{intel|Iris Graphics 550|550}}, {{intel|Iris Pro Graphics P555|P555}} || {{intel|Iris Pro Graphics 580|580}}, {{intel|Iris Pro Graphics P580|P580}}
 
|-
 
| Tiers || GT1 || GT2 || GT3e || GT4e || GT1 || GT2 || GT3e || GT4e ||  GT1 || GT2 || GT3e || GT4e
 
|-
 
| Ref (FLOP/clk) || 384/cycle || 768/cycle || 1536/cycle || 2304/cycle || 192/cycle || 384/cycle || 768/cycle || 1152/cycle || 48/cycle || 96/cycle || 192/cycle || 288/cycle
 
|-
 
| Base (300 MHz) || {{#expr: 384*.3}} [[GFLOPS]] || {{#expr: 768*.3}} GFLOPS || {{#expr: 1536*.3}} GFLOPS || {{#expr: 2304*.3}} GFLOPS || {{#expr: 192*.3}} GFLOPS || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 1152*.3}} GFLOPS || {{#expr: 48*.3}} GFLOPS || {{#expr: 96*.3}} GFLOPS || {{#expr: 129*.3}} GFLOPS || {{#expr: 288*.3}} GFLOPS
 
|-
 
| Base (350 MHz) || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1536*.35}} GFLOPS || {{#expr: 2304*.35}} GFLOPS || {{#expr: 192*.35}} GFLOPS || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1152*.35}} GFLOPS || {{#expr: 48*.35}} GFLOPS || {{#expr: 96*.35}} GFLOPS || {{#expr: 129*.35}} GFLOPS || {{#expr: 288*.35}} GFLOPS
 
|-
 
| Base (400 MHz) || {{#expr: 384*.4}} GFLOPS || {{#expr: 768*.4}} GFLOPS || {{#expr: 1536*.4}} GFLOPS || {{#expr: 2304*.4}} GFLOPS || {{#expr: 192*.4}} GFLOPS || {{#expr: 384*.4}} GFLOPS || {{#expr: 768*.4}} GFLOPS || {{#expr: 1152*.4}} GFLOPS || {{#expr: 48*.4}} GFLOPS || {{#expr: 96*.4}} GFLOPS || {{#expr: 129*.4}} GFLOPS || {{#expr: 288*.4}} GFLOPS
 
|-
 
| Base (650 MHz) || {{#expr: 384*.65}} GFLOPS || {{#expr: 768*.65}} GFLOPS || {{#expr: 1536*.65}} GFLOPS || {{#expr: 2304*.65}} GFLOPS || {{#expr: 192*.65}} GFLOPS || {{#expr: 384*.65}} GFLOPS || {{#expr: 768*.65}} GFLOPS || {{#expr: 1152*.65}} GFLOPS || {{#expr: 48*.65}} GFLOPS || {{#expr: 96*.65}} GFLOPS || {{#expr: 129*.65}} GFLOPS || {{#expr: 288*.65}} GFLOPS
 
|-
 
| Boost (800 MHz) || {{#expr: 384*.8}} GFLOPS || {{#expr: 768*.8}} GFLOPS || {{#expr: 1536*.8}} GFLOPS || {{#expr: 2304*.8}} GFLOPS || {{#expr: 192*.8}} GFLOPS || {{#expr: 384*.8}} GFLOPS || {{#expr: 768*.8}} GFLOPS || {{#expr: 1152*.8}} GFLOPS || {{#expr: 48*.8}} GFLOPS || {{#expr: 96*.8}} GFLOPS || {{#expr: 129*.8}} GFLOPS || {{#expr: 288*.8}} GFLOPS
 
|-
 
| Boost (850 MHz) || {{#expr: 384*.85}} GFLOPS || {{#expr: 768*.85}} GFLOPS || {{#expr: 1536*.85}} GFLOPS || {{#expr: 2304*.85}} GFLOPS || {{#expr: 192*.85}} GFLOPS || {{#expr: 384*.85}} GFLOPS || {{#expr: 768*.85}} GFLOPS || {{#expr: 1152*.85}} GFLOPS || {{#expr: 48*.85}} GFLOPS || {{#expr: 96*.85}} GFLOPS || {{#expr: 129*.85}} GFLOPS || {{#expr: 288*.85}} GFLOPS
 
|-
 
| Boost (900 MHz) || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{#expr: 1536*.9}} GFLOPS || {{#expr: 2304*.9}} GFLOPS || {{#expr: 192*.9}} GFLOPS || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{#expr: 1152*.9}} GFLOPS || {{#expr: 48*.9}} GFLOPS || {{#expr: 96*.9}} GFLOPS || {{#expr: 129*.9}} GFLOPS || {{#expr: 288*.9}} GFLOPS
 
|-
 
| Boost (950 MHz) || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{#expr: 1536*.95}} GFLOPS || {{#expr: 2304*.95}} GFLOPS || {{#expr: 192*.95}} GFLOPS || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{#expr: 1152*.95}} GFLOPS || {{#expr: 48*.95}} GFLOPS || {{#expr: 96*.95}} GFLOPS || {{#expr: 129*.95}} GFLOPS || {{#expr: 288*.95}} GFLOPS
 
|-
 
| Boost (1,000 MHz) || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{#expr: 1536*1}} GFLOPS || {{#expr: 2304*1}} GFLOPS || {{#expr: 192*1}} GFLOPS || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{#expr: 1152*1}} GFLOPS || {{#expr: 48*1}} GFLOPS || {{#expr: 96*1}} GFLOPS || {{#expr: 129*1}} GFLOPS || {{#expr: 288*1}} GFLOPS
 
|-
 
| Boost (1,050 MHz) || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{#expr: 1536*1.05}} GFLOPS || {{#expr: 2304*1.05}} GFLOPS || {{#expr: 192*1.05}} GFLOPS || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{#expr: 1152*1.05}} GFLOPS || {{#expr: 48*1.05}} GFLOPS || {{#expr: 96*1.05}} GFLOPS || {{#expr: 129*1.05}} GFLOPS || {{#expr: 288*1.05}} GFLOPS
 
|-
 
| Boost (1,100 MHz) || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{#expr: 1536*1.1}} GFLOPS || {{#expr: 2304*1.1}} GFLOPS || {{#expr: 192*1.1}} GFLOPS || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{#expr: 1152*1.1}} GFLOPS || {{#expr: 48*1.1}} GFLOPS || {{#expr: 96*1.1}} GFLOPS || {{#expr: 129*1.1}} GFLOPS || {{#expr: 288*1.1}} GFLOPS
 
|-
 
| Boost (1,150 MHz) || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{#expr: 1536*1.15}} GFLOPS || {{#expr: 2304*1.15}} GFLOPS || {{#expr: 192*1.15}} GFLOPS || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{#expr: 1152*1.15}} GFLOPS || {{#expr: 48*1.15}} GFLOPS || {{#expr: 96*1.15}} GFLOPS || {{#expr: 129*1.15}} GFLOPS || {{#expr: 288*1.15}} GFLOPS
 
|}
 
</div>
 
  
 
== Hardware Accelerated Video ==
 
== Hardware Accelerated Video ==
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== Process Technology ==
 
== Process Technology ==
 
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
 
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
Gen9 are part of the Skylake SoC die which uses the same [[14 nm process]] used for the Broadwell microarchitecture.
+
Gen9 LP are part of the Skylake SoC die which uses the same [[14 nm process]] used for the Broadwell microarchitecture.
  
 
== Architecture ==
 
== Architecture ==
Gen9 presents a large departure from the Gen8 and previous architectures.
+
Gen9 LP presents a large departure from the Gen8 LP and previous architectures.
  
=== Key changes from {{\\|Gen8}} ===
+
=== Key changes from {{\\|Gen8 LP}} ===
 
* Architecture is drastically different
 
* Architecture is drastically different
** Gen9 is composed of 3 truly independent major components: Display block, Unslice, and the Slice.
+
** Gen9 LP is composed of 3 truely independent major components: Display block, Unslice, and the Slice.
 
** Shared Virtual Memory (SVM) improvements
 
** Shared Virtual Memory (SVM) improvements
 
*** Improved cache coherency performance
 
*** Improved cache coherency performance
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** RAW imaging capabilities
 
** RAW imaging capabilities
 
* Slice
 
* Slice
** Floating point atomics (min/max/cmpexch)
 
 
** L3 Cache
 
** L3 Cache
 
*** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice)
 
*** Increased to 768 [[KiB]]/slice (up from 576 KiB/slice)
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** Multi-plane overlays
 
** Multi-plane overlays
 
** Texture samplers now natively support an NV12 YUV
 
** Texture samplers now natively support an NV12 YUV
** Min/max texture filtering
 
 
** Preemption of execution is now supported at the thread level
 
** Preemption of execution is now supported at the thread level
 
** Round robin scheduling of threads within an execution unit.
 
** Round robin scheduling of threads within an execution unit.
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** 16-bit floating point capability is improved with native support for denormals and gradual underflow
 
** 16-bit floating point capability is improved with native support for denormals and gradual underflow
 
* L4$
 
* L4$
** The [[eDRAM]] is now a side cache instead of an L4$ like it was in {{\\|Gen8}}. (See {{\\|Skylake#eDRAM architectural changes|Skylake §eDRAM architectural changes}} for the reason)
+
** The [[eDRAM]] is now a side cache instead of an L4$ like it was in {{\\|Gen8 LP}}. (See {{\\|Skylake#eDRAM architectural changes|Skylake §eDRAM architectural changes}} for the reason)
 
** Side-cache eDRAM was moved into the system agent adjacent to the display controller
 
** Side-cache eDRAM was moved into the system agent adjacent to the display controller
  
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==== Entire SoC Overview ====
 
==== Entire SoC Overview ====
 
[[File:skylake soc block diagram.svg|900px]]
 
[[File:skylake soc block diagram.svg|900px]]
==== Gen9 ====
+
==== Gen9 LP ====
 
This block is for the most common setup, which is GT2 with 24 execution units.
 
This block is for the most common setup, which is GT2 with 24 execution units.
  
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==== Individual Core ====
 
==== Individual Core ====
 
See {{intel|Skylake#Individual_Core|l=arch}}.
 
See {{intel|Skylake#Individual_Core|l=arch}}.
 +
 +
=== Display ===
 +
{{empty section}}
  
 
=== Unslice ===
 
=== Unslice ===
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| Sample App2 || 17 ms || 24 ms || 240 µs || 200-430 µs
 
| Sample App2 || 17 ms || 24 ms || 240 µs || 200-430 µs
 
|}
 
|}
 
=== Display ===
 
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/270 rotations.
 
 
[[File:gen9 display block.svg|650px]]
 
 
==== Multiple Display Planes in a Pipe ====
 
[[File:gen9 display planes pipe.svg|right|550px]]
 
* Three plane sources + background
 
** All 3 are independent
 
** Fixed order (highest priority is plane3, lowest is background)
 
** Planes can be:
 
*** YUV video
 
*** RGB windows/desktop
 
** Fixed visual priority/blending order
 
** Color correction of result
 
** Two 7x5 scalers
 
*** Bind to individual planes or pipe output
 
* Intended to support various OS features such as
 
** Microsoft's MPO (Multiplane overlay support)
 
** Android's SurfaceFlinger
 
  
 
== Scalability ==
 
== Scalability ==
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=== GT1 (ULP) ===
 
=== GT1 (ULP) ===
GT1 is the most compact configuration offering two benefits: reduced cost and reduced power. GT1 is made of 1 slice containing 2 subslices with 6 EUs/subslice for a total of 12 EUs. With the scale-down, GT1 changes the ratio to 6:1 EU:sampler ratio. Note that this does retains the same ratio of 12 texels/clock and 8 pixels/clock at the backend. This configuration is better suited for some of the low power workload (e.g. ASTC-LDR+HDR, ETC1/2 compression). Note that software stack remains unchanged compared to the larger models.
+
GT1 is the most compact configuration offering two benefits: reduced cost and reduced power. GT1 is made of 1 slice containing 2 subslices with 6 EUs/subslice for a total of 12 EUs. With the scale-down, GT1 changes the ratio to 6:1 EU:sampler ratio. Note that this does retains the same ratio of 12 texels/clock and 8 pixels/clock at the backend. This configuration is better suited for some of the low power worlkload (e.g. ASTC-LDR+HDR, ETC1/2 compression). Note that software stack remains unchanged compared to the larger models.
  
 
[[File:gen9 lp gt1 block diagram.svg|600px]]
 
[[File:gen9 lp gt1 block diagram.svg|600px]]
Line 492: Line 428:
 
|SFC Instances || 1 || 1 || 1 || 1 || 1
 
|SFC Instances || 1 || 1 || 1 || 1 || 1
 
|}
 
|}
 
== Datasheets ==
 
=== White Paper ===
 
* [[:File:The-Compute-Architecture-of-Intel-Processor-Graphics-Gen9-v1d0.pdf|The Compute Architecture of Intel Processor Graphics Gen9]]
 
 
===Programmer's Reference Manual===
 
* [[:File:intel-gfx-prm-osrc-skl-vol01-preface.pdf|Volume 1: Preface]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf|Volume 2a Addendum: Command Reference: Instructions (Command Opcodes) for the HEVC Micro-Controller (HuC)]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions.pdf|Volume 2a: Command Reference: Instructions (Command Opcodes)]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol02c-commandreference-registers-part1.pdf|Volume 2c: Command Reference: Registers Part 1 – Registers A through L]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol02c-commandreference-registers-part2.pdf|Volume 2c: Command Reference: Registers Part 2 – Registers M through Z]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol02d-commandreference-structures.pdf|Volume 2d: Command Reference: Structures]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol03-gpu overview.pdf|Volume 3: GPU Overview]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol04-configurations.pdf|Volume 4: Configurations]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol05-memory views.pdf|Volume 5: Memory Views]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol06-command stream programming.pdf|Volume 6: Command Stream Programming]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol07-3d media gpgpu.pdf|Volume 7: 3D-Media-GPGPU]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol08-media vdbox.pdf|Volume 8: Media VDBOX]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol09-media vebox.pdf|Volume 9: Media Video Enhancement (VEBOX) Engine]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol10-hevc.pdf|Volume 10: HEVC Codec Pipeline (HCP)]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol11-blitter.pdf|Volume 11: Blitter]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol12-display.pdf|Volume 12: Display]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol13-mmio.pdf|Volume 13: Memory-mapped Input/Output (MMIO)]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol14-observability.pdf|Volume 14: Observability]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol15-sfc.pdf|Volume 15: Scaler Format Converter (SFC)]]
 
* [[:File:intel-gfx-prm-osrc-skl-vol16-workarounds 0.pdf|Volume 16: Workarounds]]
 

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codenameGen9 +
designerIntel +
first launchedAugust 5, 2015 +
full page nameintel/microarchitectures/gen9 +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeGPU +
nameGen9 +
process14 nm (0.014 μm, 1.4e-5 mm) +