From WikiChip
Editing intel/microarchitectures/gen9
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 203: | Line 203: | ||
The '''media general-purpose pipeline''' consists of two fixed-function units: Video Front End ('''VFE''') and the '''Thread Spawner''' ('''TS'''). The VFE unit handles the interfacing with the Command Streamer, writes thread payload data into the Unified Return Buffer, as well as prepares threads to be dispatched through TS unit. The VFE unit also contains the hardware '''Variable Length Decode''' ('''VLD''') engine for MPEG-2 video decode. The TS unit is primarily responsible for interfacing with the '''Thread Dispatcher''' ('''TD''') unit which is responsible for spawning new root-node parent threads originated from VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). | The '''media general-purpose pipeline''' consists of two fixed-function units: Video Front End ('''VFE''') and the '''Thread Spawner''' ('''TS'''). The VFE unit handles the interfacing with the Command Streamer, writes thread payload data into the Unified Return Buffer, as well as prepares threads to be dispatched through TS unit. The VFE unit also contains the hardware '''Variable Length Decode''' ('''VLD''') engine for MPEG-2 video decode. The TS unit is primarily responsible for interfacing with the '''Thread Dispatcher''' ('''TD''') unit which is responsible for spawning new root-node parent threads originated from VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== 3D Pipeline Stages === | === 3D Pipeline Stages === |
Facts about "Gen9 - Microarchitectures - Intel"
codename | Gen9 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/gen9 + |
instance of | microarchitecture + |
manufacturer | Intel + |
microarchitecture type | GPU + |
name | Gen9 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |