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Difference between revisions of "intel/microarchitectures/cooper lake"
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(Key changes from {{\\|Cascade Lake}})
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=== Key changes from {{\\|Cascade Lake}} ===
 
=== Key changes from {{\\|Cascade Lake}} ===
 
* SoC
 
* SoC
** Higher core count (??, up from [[28 cores|28]])
+
** ?
 
* Memory
 
* Memory
 
** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
 
** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
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*** Apache Pass '''→''' Barlow Pass
 
*** Apache Pass '''→''' Barlow Pass
 
* Platform
 
* Platform
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
+
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} (mainstream)
 +
** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} (AP)
 
* Packaging
 
* Packaging
 
** 4189-contact flip-chip LGA (up from 3647 contacts)
 
** 4189-contact flip-chip LGA (up from 3647 contacts)

Revision as of 02:14, 17 July 2019

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Coffee Lake

Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers.

For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.


Codenames

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates

Cooper Lake and Ice Lake roadmap.

Cooper Lake is expected to be released in the first half of 2020.

Process Technology

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture

Cooper Lake is based on the Whitley platform.

Key changes from Cascade Lake

  • SoC
    •  ?
  • Memory
    • Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
    • Octa-channel (up from hexa-channel)
    • Optane DC DIMMs
      • Apache Pass Barlow Pass
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Cooper Lake introduced a number of new instructions:

See also

codenameCooper Lake +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +