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| − | {{intel title|Coffee Lake|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Coffee Lake
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |introduction=October 5, 2017
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| − | |process=14 nm
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| − | |cores=4
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| − | |cores 2=6
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |stages min=14
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| − | |stages max=19
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| − | |decode=5-way
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| − | |isa=x86-16
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| − | |isa 2=x86-32
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| − | |isa 3=x86-64
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| − | |extension=MOVBE
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| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4.1
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| − | |extension 8=SSE4.2
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| − | |extension 9=POPCNT
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| − | |extension 10=AVX
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| − | |extension 11=AVX2
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| − | |extension 12=AES
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| − | |extension 13=PCLMUL
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| − | |extension 14=FSGSBASE
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| − | |extension 15=RDRND
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| − | |extension 16=FMA3
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| − | |extension 17=F16C
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| − | |extension 18=BMI
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| − | |extension 19=BMI2
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| − | |extension 20=VT-x
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| − | |extension 21=VT-d
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| − | |extension 22=TXT
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| − | |extension 23=TSX
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| − | |extension 24=RDSEED
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| − | |extension 25=ADCX
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| − | |extension 26=PREFETCHW
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| − | |extension 27=CLFLUSHOPT
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| − | |extension 28=XSAVE
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| − | |extension 29=SGX
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| − | |extension 30=MPX
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| − | |l1i=32 KiB
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| − | |l1i per=core
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| − | |l1i desc=8-way set associative
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| − | |l1d=32 KiB
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| − | |l1d per=core
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| − | |l1d desc=8-way set associative
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| − | |l2=256 KiB
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| − | |l2 per=core
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| − | |l2 desc=4-way set associative
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| − | |l3=2 MiB
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| − | |l3 per=core
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| − | |l3 desc=Up to 16-way set associative
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| − | |l4=128 MiB
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| − | |l4 per=package
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| − | |l4 desc=on Iris Pro GPUs only
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| − | |core name=Coffee Lake U
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| − | |core name 2=Coffee Lake H
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| − | |core name 3=Coffee Lake S
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| − | |predecessor=Kaby Lake
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| − | |predecessor link=intel/microarchitectures/kaby lake
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| − | |successor=Cannonlake
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| − | |successor link=intel/microarchitectures/cannonlake
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| − | }}
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| − | '''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel.
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| | | | |
| − | == Codenames ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Core !! Abbrev !! Description !! Graphics !! Target
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| − | |-
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| − | | {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
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| − | |-
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| − | | {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT3e || Ultimate mobile performance, mobile workstations
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| − | |-
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| − | | {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
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| − | |-
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| − | | {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops
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| − | |}
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| − |
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| − | == Brands ==
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| − | Intel released Coffee Lake under 3 main brand families:
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| − |
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| − | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
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| − | |-
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| − | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
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| − | |-
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| − | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
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| − | |-
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| − | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
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| − | |-
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| − | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| − | |-
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| − | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| − | |}
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| − |
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| − | == Release Dates ==
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| − | [[File:2016 to 2018 kaby cannon coffee roadmap.jpg|left|300px]]
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| − | Early roadmaps indicated Coffee Lake was to be introduced around the second quarter of 2018. In early 2017 Intel announced that 8th generation processors will be available starting from the 3rd quarter of 2017. While the exact reason for the early release is unknown, it seems likely to attribute the move to various market forces, particularly AMD's introduction of {{amd|Zen|l=arch}} and the {{amd|Ryzen}} family.
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| − |
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| − | Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.
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| − |
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| − | {{clear}}
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| − |
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| − | == Technology ==
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| − | [[File:intel 14nm++.png|400px|right]]
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| − | {{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
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| − | Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides 26% more performance for 52% less power.
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| − |
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| − |
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| − | [[File:intel 14nm++ (nmos).png|400px]]
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| − | [[File:intel 14nm++ (pmos).png|400px]]
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| − |
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| − |
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| − | Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). There is no real density change despite this change likely due to various design techniques such as reduced fins where unnecessary.
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| − |
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| − | {| class="wikitable"
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| − | |-
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| − | ! !! Kaby Lake !! Coffee Lake !! Δ
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| − | |-
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| − | | || [[14 nm]] || 14 nm ||
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| − | |-
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| − | | Gate Pitch || 70 nm || 84 nm || 1.20x
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| − | |-
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| − | | Interconnect Pitch || 52 nm || 52 nm || 1.00x
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| − | |}
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| − |
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| − | {{clear}}
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| − |
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| − | == Compatibility==
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| − | {{empty section}}
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| − |
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| − | == Compiler support ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Compiler !! Arch-Specific || Arch-Favorable
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| − | |-
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| − | | [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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| − | |-
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| − | | [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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| − | |-
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| − | | [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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| − | |-
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| − | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
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| − | |}
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| − |
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| − | === CPUID ===
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| − | {| class="wikitable tc1 tc2 tc3 tc4"
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| − | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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| − | |-
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| − | | rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x9 || 0xE
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| − | |-
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| − | | colspan="4" | Family 6 Model 158
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| − | |-
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| − | | rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x? || 0x?
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| − | |-
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| − | | colspan="4" | Family 6 Model ???
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| − | |}
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| − |
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| − | == Architecture ==
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| − | [[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]]
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| − | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]].
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| − |
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| − | === Key changes from {{\\|Kaby Lake}}===
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| − | * Enhanced "14nm++" process results in higher turbo frequencies
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| − | * IPC improvement from larger cache for various workloads, but actual core is unchanged
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| − |
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| − | * System Architecture
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| − | ** 50% more [[physical core|cores]] (6, from 4)
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| − | ** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
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| − |
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| − | * Core
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| − | ** LSD has been re-enabled (Previously {{\\|skylake_(server)#Front-end|disabled}})
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| − |
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| − | * Chipset
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| − | ** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset (Cannonlake PCH)<!--
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| − | *** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
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| − | *** Soundwire Digital Audio Interface
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| − | *** Integrated USB 3.1 (10 Gib/s)
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| − | **** Up to 6 ports
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| − | *** Integrated Intel wireless controller ([[IEEE 802.11ac]])
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| − | *** Integrated SDXC 3.0 controller
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| − | *** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
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| − | *** C10 & S0ix Support for Modern Standby-->
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| − |
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| − | * Memory
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| − | ** Faster memory for mainstream desktops (i.e., {{intel|Coffee Lake S|l=core}}) DDR4-2666 (from DDR4-2400)
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| − |
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| − | * Graphics
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| − | ** {{intel|Gen 9.5|l=arch}} GPUs (No Change)
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| − | ** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only)
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| − | *** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change)
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| − |
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| − | * Families
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| − | ** {{intel|Core i3}} gained 100% more [[physical core|cores]] (4, from 2) but dropped {{intel|hyper-threading}} support
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| − | ** {{intel|Core i5}} gained 50% more cores (6, from 4)
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| − | ** {{intel|Core i7}} gained 50% more cores (6, from 4)
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| − |
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| − | === Block Diagram ===
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| − |
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| − | ====== Entire SoC Overview (quad) ======
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| − | [[File:kaby lake soc block diagram.svg|800px]]
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| − |
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| − | ==== Entire SoC Overview (hexa) ====
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| − | [[File:coffee lake soc block diagram.svg|900px]]
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| − |
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| − | ==== Individual Core ====
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| − | <small>(Core identical to {{\\|Skylake (client)}})</small>
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| − |
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| − | [[File:skylake block diagram.svg|900px]]
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| − |
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| − | ==== Gen9.5 ====
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| − | See {{intel|Gen9.5#Gen9.5|l=arch}}.
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| − |
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| − | === Memory Hierarchy ===
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| − | The overall memory structure is identical to {{\\|Skylake}}.
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| − |
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| − | <!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
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| − | * Cache
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| − | ** L0 µOP cache:
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| − | *** 1,536 µOPs, 8-way set associative
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| − | **** 32 sets, 6-µOP line size
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| − | **** statically divided between threads, per core, inclusive with L1I
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| − | ** L1I Cache:
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| − | *** 32 [[KiB]], 8-way set associative
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| − | **** 64 sets, 64 B line size
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| − | **** shared by the two threads, per core
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| − | ** L1D Cache:
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| − | *** 32 KiB, 8-way set associative
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| − | *** 64 sets, 64 B line size
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| − | *** shared by the two threads, per core
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| − | *** 4 cycles for fastest load-to-use (simple pointer accesses)
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| − | **** 5 cycles for complex addresses
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| − | *** 64 B/cycle load bandwidth
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| − | *** 32 B/cycle store bandwidth
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| − | *** Write-back policy
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| − | ** L2 Cache:
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| − | *** Unified, 256 KiB, 4-way set associative
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| − | *** Non-inclusive
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| − | *** 1024 sets, 64 B line size
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| − | *** 12 cycles for fastest load-to-use
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| − | *** 64 B/cycle bandwidth to L1$
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| − | *** Write-back policy
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| − | ** L3 Cache/LLC:
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| − | *** Up to 2 MiB Per core, shared across all cores
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| − | *** Up to 16-way set associative
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| − | *** Inclusive
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| − | *** 64 B line size
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| − | *** Write-back policy
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| − | *** Per each core:
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| − | **** Read: 32 B/cycle (@ ring [[clock]])
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| − | **** Write: 32 B/cycle (@ ring clock)
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| − | *** 42 cycles for fastest load-to-use
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| − | ** Side Cache:
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| − | *** 64 MiB & 128 MiB [[eDRAM]]
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| − | *** Per package
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| − | *** Only on the Iris Pro GPUs
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| − | *** Read: 32 B/cycle (@ [[eDRAM]] clock)
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| − | *** Write: 32 B/cycle (@ eDRAM clock)
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| − | ** System [[DRAM]]:
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| − | *** 2 Channels
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| − | *** 8 B/cycle/channel (@ memory clock)
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| − | *** 42 cycles + 51 ns latency
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| − |
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| − | Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
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| − | * TLBs:
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| − | ** ITLB
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| − | *** 4 KiB page translations:
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| − | **** 128 entries; 8-way set associative
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| − | **** dynamic partitioning
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| − | *** 2 MiB / 4 MiB page translations:
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| − | **** 8 entries per thread; fully associative
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| − | **** Duplicated for each thread
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| − | ** DTLB
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| − | *** 4 KiB page translations:
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| − | **** 64 entries; 4-way set associative
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| − | **** fixed partition
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| − | *** 2 MiB / 4 MiB page translations:
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| − | **** 32 entries; 4-way set associative
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| − | **** fixed partition
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| − | *** 1G page translations:
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| − | **** 4 entries; fully associative
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| − | **** fixed partition
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| − | ** STLB
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| − | *** 4 KiB + 2 MiB page translations:
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| − | **** 1536 entries; 12-way set associative
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| − | **** fixed partition
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| − | *** 1 GiB page translations:
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| − | **** 16 entries; 4-way set associative
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| − | **** fixed partition
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| − | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
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| − |
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| − |
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| − | * '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.
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| − |
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| − | == Overview ==
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| − | [[File:coffee lake overview.svg|right|500px]]
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| − | The Coffee Lake system on a chip consists of a five major components: CPU [[physical core|cores]], [[last level cache|LLC]], Ring interconnect, {{intel|System Agent}}, and the [[integrated graphics]]. The core architecture in Coffee Lake, like in {{\\|Kaby Lake}}, as not changed from {{\\|Skylake}}. This is also true for the integrated graphics which is identical to the one incorporated in {{\\|Kaby Lake}} and from a platform point of view, the I/O has not changed (supporting up to 3 displays and providing 16 PCIe Gen 3 lanes). Coffee Lake, however, has brought a relatively large change to the overall system architecture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for up to 4 MiB of additional [[last level cache]]).
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| − |
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| − | In addition to improving multi-thread performance considerably by introducing 50% or two more cores as well as up to four additional threads, the added addition of up to 4 MiB of cache should have a positive impact on most single-thread performance.
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| − |
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| − | === Historical Trend ===
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| − | Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecutre since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 Extreme based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent).
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| − |
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| − |
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| − | ::[[File:penryn-nehalem overview change.svg|500px|left]]
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| − |
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| − |
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| − | With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge.
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| − | [[File:sandy bridge ring scalability.svg|right|100px]]
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| − | Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.
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| − |
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| − |
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| − | ::[[File:nehalem-sandy bridge overview change.svg|500px|right]]
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| − |
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| − |
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| − | From {{\\|Sandy Bridge}} through [[22 nm]] {{\\|Haswell}} and through [[14 nm]] {{\\|Skylake}}, the [[die shrink|die shrunk]] considerably, even after {{\\|skylake_(client)#Key_changes_from_Broadwell|large amount of enhancements}} (and thus transistors) were done to the microarchitecture. With the aid of [[Moore's Law]], the [[quad-core]] die in Coffee Lake's predecessor, {{\\|Kaby Lake}}, has reached 126 mm² - 42% smaller than the quad-core Sandy Bridge while packing over 3 times as much transistors.
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| − |
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| − | Since Coffee Lake utilizes Intel's 3rd generation enhanced [[14 nm process|14nm++ process]] which has reached maturity and healthy yield, Intel can afford to increase the amount of cores by 50% from [[4 cores|4]] to [[6 cores]]. This is also possible thanks to the existing ring interconnect that was designed specifically to be able to support this configuration. In addition to the two added cores, there are two addition LLC slices - each consisting of 2 MiB in size.
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| − |
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| − |
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| − | ::[[File:sandy bridge-coffee lake overview change.svg|500px|left]]
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| − |
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| − |
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| − | [[File:quad to hexa mainstream die areas.svg|500px|right]]
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| − | It can easily be seen how the natural evolution of [[Moore's Law]] and its affects on the die size of Intel's mainstream platform enables the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices contributed an extra ~25mm². In fact, it can further be seen that even an 8-core Coffee Lake would be smaller than Haswell's quad-core at around 174 mm². It's worth noting that Coffee Lake is released concurrently with {{\\|Cannonlake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well.
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| − |
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| − | {{clear}}
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| − |
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| − | == Core ==
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| − | === Pipeline ===
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| − | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
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| − | Coffee Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.
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| − |
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| − | ==== Front-end ====
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| − | Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}.
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| − |
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| − | ==== Scheduler Ports & Execution Units ====
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| − | <table class="wikitable">
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| − | <tr><th colspan="2">Scheduler Ports Designation</th></tr>
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| − | <tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr>
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| − | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
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| − | <tr><td>Integer/FP Division and [[Square Root]]</td></tr>
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| − | <tr><td>[[AES]] Encryption</td></tr>
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| − | <tr><td>Branch2</td></tr>
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| − | <tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr>
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| − | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
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| − | <tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr>
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| − | <tr><td>Vector Permute</td></tr>
| |
| − | <tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr>
| |
| − | <tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr>
| |
| − | <tr><td>Branch</td></tr>
| |
| − | <tr><th>Port 2</th><td>Load, AGU</td></tr>
| |
| − | <tr><th>Port 3</th><td>Load, AGU</td></tr>
| |
| − | <tr><th>Port 4</th><td>Store, AGU</td></tr>
| |
| − | <tr><th>Port 7</th><td>AGU</td></tr>
| |
| − | </table>
| |
| − |
| |
| − | {| class="wikitable collapsible collapsed"
| |
| − | |-
| |
| − | ! colspan="3" | Execution Units
| |
| − | |-
| |
| − | ! Execution Unit !! # of Units !! Instructions
| |
| − | |-
| |
| − | | ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
| |
| − | |-
| |
| − | | DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
| |
| − | |-
| |
| − | | Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc...
| |
| − | |-
| |
| − | | Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
| |
| − | |-
| |
| − | | Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc...
| |
| − | |-
| |
| − | | Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc
| |
| − | |-
| |
| − | | FP Mov || 1 || (v)movsd/ss, (v)movd gpr
| |
| − | |-
| |
| − | | SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
| |
| − | |-
| |
| − | | Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
| |
| − | |-
| |
| − | | Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8
| |
| − | |-
| |
| − | | Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
| |
| − | |-
| |
| − | | Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd*
| |
| − | |-
| |
| − | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
| |
| − | |}
| |
| − |
| |
| − | == Configurability ==
| |
| − | Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die. Currently the Coffee Lake family consists out of two dies, aimed towards the high performance market.
| |
| − |
| |
| − | <gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left">
| |
| − | File:4 core hp gt2 skylake.svg|Quad-core die, GT2 GPU, High Power
| |
| − | File:6 core hp gt2 coffeelake.svg|Hexa-core die, GT2 GPU, High Power
| |
| − | </gallery>
| |
| − |
| |
| − | {{clear}}
| |
| − |
| |
| − | == Graphics ==
| |
| − | {{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
| |
| − | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, and [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Coffee Lake's graphics are identical to Kaby Lake and have native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).
| |
| − |
| |
| − | {| class="wikitable tc2 tc3"
| |
| − | |-
| |
| − | ! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards
| |
| − | |-
| |
| − | ! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !! rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
| |
| − | |-
| |
| − | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
| |
| − | |-
| |
| − | | {{intel|UHD Graphics 630}} || 23/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0'''
| |
| − | |}
| |
| − |
| |
| − | <references group=graphics />
| |
| − | ==== Hardware Accelerated Video ====
| |
| − | {{coffee lake hardware accelerated video table}}
| |
| − |
| |
| − | == Power delivery ==
| |
| − | Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake break compatibility with {{\\|Skylake (client)|Skylake}} and {{\\|Kaby Lake}} due to various enhancements to the power delivery of the processor in order to better handle the additional cores.
| |
| − |
| |
| − | In order to improve the power delivery of the chip and support higher package-level current delivered for the additional cores, Intel needed to increase the number of pins that go to the power rails of the die. Since there is a practical limit as to how much current each pin is capable of delivering, a large number of additional pins that were previously unused/reserved have also been allocated for this purpose. The new hexa-core parts have 38 higher amperage rating.
| |
| − |
| |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | ! colspan="3" | Pin Changes
| |
| − | |-
| |
| − | ! || Skylake/Kaby Lake || Coffee Lake
| |
| − | |-
| |
| − | ! Socket || FCLGA-1151 || FCLGA-1151
| |
| − | |-
| |
| − | | Contacts || 1151 || 1151
| |
| − | |-
| |
| − | | Reserved Pins || 46 || 25 (-21)
| |
| − | |-
| |
| − | | VSS (Ground) || 377 || 391 (+14)
| |
| − | |-
| |
| − | | VCC (Power) || 128 || 146 (+18)
| |
| − | |-
| |
| − | | rowspan="8" | Core I<sub>cc</sub> || rowspan="2" | || 138 A (Hexa; 95 W)
| |
| − | |-
| |
| − | | 133 A (Hexa; 65 W)
| |
| − | |-
| |
| − | | 100 A (Quad; 91 W) || 100 A (Quad; 95 W)
| |
| − | |-
| |
| − | | 79 A (Quad; 65 W) || 79 A (Quad; 65 W)
| |
| − | |-
| |
| − | | 66 A (Quad; 35 W)
| |
| − | |-
| |
| − | | 58 A (Dual; 54 W)
| |
| − | |-
| |
| − | | 45 A (Dual; 51 W)
| |
| − | |-
| |
| − | | 40 A (Dual; 35 W)
| |
| − | |-
| |
| − | | Pinout || [[File:skylake pin diagram.png|350px]] || [[File:coffee lake pin diagram.png|350px]]
| |
| − | |}
| |
| − |
| |
| − | == Die ==
| |
| − | Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are:
| |
| − |
| |
| − | * System Agent
| |
| − | * CPU Core
| |
| − | * Ring bus interconnect
| |
| − | * Memory Interface
| |
| − |
| |
| − | === System Agent ===
| |
| − | The System Agent (SA) contains the Display Engine (DE) and the I/O bus.
| |
| − |
| |
| − | <div style="text-align: center; display: inline-block;">
| |
| − | '''Hexa-Core Die'''
| |
| − | <div style="float: left; margin: 10px;">[[File:coffee lake 6c sa.png|150px]]</div>
| |
| − | <div style="float: left; margin: 10px;">[[File:coffee lake 6c sa (annotated).png|150px]]</div>
| |
| − | </div>
| |
| − |
| |
| − | {{clear}}
| |
| − |
| |
| − | === Integrated Graphics ===
| |
| − | The [[integrated graphics]] makes up a large portion of the die. The normal [[dual-core]] and [[quad-core]] dies come with 24 EU {{\\|Gen9.5}} GPU (with 12 units disabled on the low end models).
| |
| − |
| |
| − | <div style="text-align: center; display: inline-block;">
| |
| − | <div style="float: left; margin: 10px;">[[File:coffee lake gpu.png|350px]]</div>
| |
| − | <div style="float: left; margin: 10px;">[[File:coffee lake gpu (annotated).png|390px]]</div>
| |
| − | </div>
| |
| − |
| |
| − | === Quad-Core ===
| |
| − | * [[14 nm process|14 nm++ process]]
| |
| − | * 11 metal layers
| |
| − | * 126 mm² die size
| |
| − | * 4 CPU cores + 23 GPU EUs
| |
| − |
| |
| − | === Hexa-Core ===
| |
| − | * [[14 nm process|14 nm++ process]]
| |
| − | * 11 metal layers
| |
| − | * 149 mm² die size
| |
| − | * 6 CPU cores + 24 GPU EUs
| |
| − |
| |
| − |
| |
| − | : [[File:coffee lake die (hexa core).png|650px]]
| |
| − |
| |
| − |
| |
| − | : [[File:coffee lake die (quad core) (annotated).png|650px]]
| |
| − |
| |
| − | === Additional Shots ===
| |
| − | Additional die and wafer shots provided by Intel:
| |
| − |
| |
| − | <gallery mode=slideshow>
| |
| − | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies.
| |
| − | </gallery>
| |
| − |
| |
| − | == All Coffee Lake Chips ==
| |
| − | <!-- NOTE:
| |
| − | This table is generated automatically from the data in the actual articles.
| |
| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
| |
| − | created and tagged accordingly.
| |
| − |
| |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| |
| − | -->
| |
| − | {{comp table start}}
| |
| − | <table class="comptable sortable tc7 tc8 tc20 tc21">
| |
| − | {{comp table header|main|20:List of Coffee Lake-based Processors}}
| |
| − | {{comp table header|main|10:Main processor|4:{{intel|Turbo Boost}}|Memory|3:GPU|2:Features}}
| |
| − | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|1 Core|2 Cores|4 Cores|6 Cores|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}
| |
| − | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]
| |
| − | |?full page name
| |
| − | |?model number
| |
| − | |?first launched
| |
| − | |?release price
| |
| − | |?microprocessor family
| |
| − | |?platform
| |
| − | |?core name
| |
| − | |?core count
| |
| − | |?thread count
| |
| − | |?l3$ size
| |
| − | |?tdp
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency (1 core)#GHz
| |
| − | |?turbo frequency (2 cores)#GHz
| |
| − | |?turbo frequency (4 cores)#GHz
| |
| − | |?turbo frequency (6 cores)#GHz
| |
| − | |?max memory#GiB
| |
| − | |?integrated gpu
| |
| − | |?integrated gpu base frequency
| |
| − | |?integrated gpu max frequency
| |
| − | |?has intel turbo boost technology 2_0
| |
| − | |?has simultaneous multithreading
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |userparam=22:21
| |
| − | |mainlabel=-
| |
| − | }}
| |
| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}}
| |
| − | </table>
| |
| − | {{comp table end}}
| |
| − |
| |
| − | == Documents ==
| |
| − | * [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
| |
| − | * [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]]
| |
| − | * [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]]
| |
| − |
| |
| − | == References ==
| |
| − | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
| |
| − | * Intel 8th Generation Core announcement, Sept 25, 2017.
| |
