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*** 100% more [[physical core|cores]] (8, from 4) | *** 100% more [[physical core|cores]] (8, from 4) | ||
*** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB) | *** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB) | ||
+ | |||
+ | * Core | ||
+ | ** LSD has been re-enabled (Previously {{\\|skylake_(server)#Front-end|disabled}}) | ||
* Chipset | * Chipset | ||
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==== Front-end ==== | ==== Front-end ==== | ||
− | + | Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}. | |
− | |||
==== Scheduler Ports & Execution Units ==== | ==== Scheduler Ports & Execution Units ==== |
Facts about "Coffee Lake - Microarchitectures - Intel"
codename | Coffee Lake + |
designer | Intel + |
first launched | October 5, 2017 + |
full page name | intel/microarchitectures/coffee lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + and dell + |
microarchitecture type | CPU + |
name | Coffee Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |