From WikiChip
Difference between revisions of "intel/microarchitectures/cascade lake"
< intel‎ | microarchitectures

(Replaced content with "DICK IS YuMMY")
Line 1: Line 1:
 
DICK IS YuMMY
 
DICK IS YuMMY
 +
very good taste

Revision as of 09:28, 11 January 2020

DICK IS YuMMY very good taste

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cascade_lake&oldid=95478"
Facts about "Cascade Lake - Microarchitectures - Intel"
RDF feed
codenameCascade Lake +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cascade lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCascade Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +