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Although Optane DC DIMMs are DDR4 pin-compatible, meaning they use the same electrical and mechanical interface as DDR4, they are not a direct drop-in replacement. Those DIMMs have different characteristics and therefore they interface with the CPU over proprietary protocol extensions. For this reason, Cascade Lake features an overhauled memory controller capable of interfacing with both DDR4 DIMMs and Optane DC DIMMs. Memory channels can be shared between DDR4 and Optane DC modules. For example, a single channel can have one regular DDR4 DIMM while the other DIMM can be an Optane DC DIMM. All in all, Optane DC DIMMs allow for greater than 3 TiB of system memory per socket.
 
Although Optane DC DIMMs are DDR4 pin-compatible, meaning they use the same electrical and mechanical interface as DDR4, they are not a direct drop-in replacement. Those DIMMs have different characteristics and therefore they interface with the CPU over proprietary protocol extensions. For this reason, Cascade Lake features an overhauled memory controller capable of interfacing with both DDR4 DIMMs and Optane DC DIMMs. Memory channels can be shared between DDR4 and Optane DC modules. For example, a single channel can have one regular DDR4 DIMM while the other DIMM can be an Optane DC DIMM. All in all, Optane DC DIMMs allow for greater than 3 TiB of system memory per socket.
  
 +
=== Encryption ===
 
Although the instructions to support persistent memory were already introduced in {{\\|Skylake (Server)|Skylake}}, Cascade Lake can now actually make use of them. The bare minimum for persistent memory support can be realized by simply putting the data in the write pending queue (WPQ) of the integrated memory controller within the persistence domain. The persistence domain is a unique checkpoint. Once data makes it to that point, it’s persistence is guaranteed by the platform interface. This is shown in the diagram on the right in the bottom dotted box. Any data within that box is either saved on the DIMM, on the way to the DIMM, or in the WPQ in the IMC. Regardless of where it is, the platform is required to store enough energy (e.g., through on-board supercapacitors) to save everything within that box in the event of a power loss.
 
Although the instructions to support persistent memory were already introduced in {{\\|Skylake (Server)|Skylake}}, Cascade Lake can now actually make use of them. The bare minimum for persistent memory support can be realized by simply putting the data in the write pending queue (WPQ) of the integrated memory controller within the persistence domain. The persistence domain is a unique checkpoint. Once data makes it to that point, it’s persistence is guaranteed by the platform interface. This is shown in the diagram on the right in the bottom dotted box. Any data within that box is either saved on the DIMM, on the way to the DIMM, or in the WPQ in the IMC. Regardless of where it is, the platform is required to store enough energy (e.g., through on-board supercapacitors) to save everything within that box in the event of a power loss.
  
=== Encryption ===
 
 
[[File:cascade-lake-optane-dimm-encryption.png|right|thumb|PMM Encryption]]
 
[[File:cascade-lake-optane-dimm-encryption.png|right|thumb|PMM Encryption]]
 
One of the unique problems associated with persistent memory is the security of the persistent data itself. To that end, Optane DIMMs protects all data with 256b AES-XTP. There are two supported modes. The first one is memory mode where the DIMM is treated like DRAM memory (one big cache) and as such, the key is regenerated each boot and data is lost on a power cycle. The second mode is App Direct which keeps the key on a power cycle. In this mode, the passphrase must be securely stored to unlock the data. Interestingly, one of the features that are currently missing is support for any form of virtualization. Currently, in a virtualized environment, the DIMM is unlocked using a single passphrase meaning the host has access to all the data. It’s reasonable to expect that in future Xeons, support for virtualization will be added such that data can be remained encrypted and private for that VM.
 
One of the unique problems associated with persistent memory is the security of the persistent data itself. To that end, Optane DIMMs protects all data with 256b AES-XTP. There are two supported modes. The first one is memory mode where the DIMM is treated like DRAM memory (one big cache) and as such, the key is regenerated each boot and data is lost on a power cycle. The second mode is App Direct which keeps the key on a power cycle. In this mode, the passphrase must be securely stored to unlock the data. Interestingly, one of the features that are currently missing is support for any form of virtualization. Currently, in a virtualized environment, the DIMM is unlocked using a single passphrase meaning the host has access to all the data. It’s reasonable to expect that in future Xeons, support for virtualization will be added such that data can be remained encrypted and private for that VM.

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codenameCascade Lake +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cascade lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCascade Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +