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Latest revision | Your text | ||
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|l3 per=core | |l3 per=core | ||
|l3 desc=Up to 16-way set associative | |l3 desc=Up to 16-way set associative | ||
− | |core name 2=Cannon Lake | + | |core name=Cannon Lake Y |
+ | |core name 2=Cannon Lake U | ||
|predecessor=Kaby Lake | |predecessor=Kaby Lake | ||
|predecessor link=intel/microarchitectures/kaby lake | |predecessor link=intel/microarchitectures/kaby lake | ||
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|- | |- | ||
! Core !! Abbrev !! Description !! Graphics !! Target | ! Core !! Abbrev !! Description !! Graphics !! Target | ||
+ | |- | ||
+ | | {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks | ||
|- | |- | ||
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | | {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | ||
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 | + | | rowspan="2" | {{intel|Cannon Lake Y|Y|l=core}}, {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 |
|- | |- | ||
| colspan="4" | Family 6 Model 102 | | colspan="4" | Family 6 Model 102 | ||
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** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}}) | ** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}}) | ||
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}}) | ** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}}) | ||
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====New instructions ==== | ====New instructions ==== |
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |