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|l3 per=core
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
|core name 2=Cannon Lake Y
+
|core name=Cannon Lake Y
 +
|core name 2=Cannon Lake U
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
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== Codenames ==
 
== Codenames ==
 +
{{future information}}
 +
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
! Core !! Abbrev !! Description !! Graphics !! Target
 +
|-
 +
| {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
|-
 
|-
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 +
|-
 +
| {{intel|Cannon Lake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
 +
|-
 +
| {{intel|Cannon Lake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
 +
|-
 +
| {{intel|Cannon Lake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers
 
|}
 
|}
  
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
+
! !! Broadwell !! Cannon Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
 
|-
 
|-
 
| || [[14 nm]] || [[10 nm]] ||
 
| || [[14 nm]] || [[10 nm]] ||
 
|-
 
|-
| Fin Pitch || &nbsp;42 nm || &nbsp;34 nm || 0.81x
+
| Fin Pitch || 42 nm || 34 || 0.81x
 
|-
 
|-
| Fin Width​ || &nbsp;&nbsp;8 nm || &nbsp;&nbsp;7 nm || 0.88x
+
| Fin Width​ || 8 nm || 7 nm || 0.88x
 
|-
 
|-
| Fin Height​ || &nbsp;42 nm || &nbsp;53 nm || 1.24x
+
| Fin Height​ || 42 nm || 53 nm || 1.24x
 
|-
 
|-
| Gate Pitch || &nbsp;70 nm || &nbsp;54 nm || 0.77x
+
| Gate Pitch || 70 nm || 54 nm || 0.77x
 
|-
 
|-
| Interconnect Pitch || &nbsp;52 nm || &nbsp;36 nm || 0.69x
+
| Interconnect Pitch || 52 nm || 36 nm || 0.69x
 
|-
 
|-
 
| Cell Height || 399 nm || 272 nm || 0.68x
 
| Cell Height || 399 nm || 272 nm || 0.68x
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
| rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
+
| rowspan="2" | {{intel|Cannon Lake Y|Y|l=core}}, {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
 
|-
 
|-
 
| colspan="4" | Family 6 Model 102
 
| colspan="4" | Family 6 Model 102
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== Architecture ==
 
== Architecture ==
=== Key changes from {{\\|Skylake (client)|Skylake}} ===
+
{{empty section}}
 +
=== Key changes from {{\\|Skylake}}/{{\\|Kaby Lake|KBL}}/{{\\|Coffee Lake|CFL}} ===
 
* [[10 nm process]] (from [[14 nm]])
 
* [[10 nm process]] (from [[14 nm]])
 
* {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
 
** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
 
 
 
* Mainstream chipset
 
* Mainstream chipset
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
+
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}<!--
 +
*** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
 +
*** Soundwire Digital Audio Interface
 +
*** Integrated USB 3.1 (10 Gib/s)
 +
**** Up to 6 ports
 +
*** Integrated Intel wireless controller ([[IEEE 802.11ac]])
 +
*** Integrated SDXC 3.0 controller
 +
*** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
 +
*** C10 & S0ix Support for Modern Standby-->
  
 
* Mobile Processors
 
* Mobile Processors
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* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen10|l=arch}} GPUs
 
* {{intel|Gen10|l=arch}} GPUs
** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
+
** {{intel|HD Graphics 610}} '''→''' {{intel|UHD Graphics 710}} (24 Execution Units, 2x EUs from {{\\|Kaby Lake}})
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
+
** {{intel|HD Graphics 615}} '''→''' {{intel|UHD Graphics 715}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 +
** {{intel|HD Graphics 620}} '''→''' {{intel|UHD Graphics 720}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 +
** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 +
** {{intel|HD Graphics P630}} '''→''' {{intel|UHD Graphics P730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 +
** {{intel|Iris Plus Graphics 640}} '''→''' {{intel|Iris Plus Graphics 740}} (unknown change)
 +
** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change)
  
* New Integration
+
==== New instructions ====
** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
+
Cannon Lake introduced a number of {{x86|extensions|new instructions}}:
  
====New instructions ====
+
* {{x86|AVX-512|<code>AVX-512</code>}}, specifically:
Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details.
+
** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation
 +
** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection
 +
** {{x86|AVX512BW|<code>AVX512BW</code>}} - AVX-512 Byte and Word
 +
** {{x86|AVX512DQ|<code>AVX512DQ</code>}} - AVX-512 Doubleword and Quadword
 +
** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length
 +
** {{x86|AVX512IFMA|<code>AVX512IFMA</code>}} - AVX-512 Integer Fused Multiply-Add
 +
** {{x86|AVX512VBMI|<code>AVX512VBMI</code>}} - AVX-512 Vector Bit Manipulation
 +
* {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
 +
* {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension
  
 
=== Block Diagram ===
 
=== Block Diagram ===
  
==== Entire SoC Overview ====
+
====== Entire SoC Overview (dual) ======
[[File:cannon lake soc block diagram.svg|800px]]
+
[[File:cannon lake soc block diagram (dual).svg|800px]]
  
 
==== Individual Core ====
 
==== Individual Core ====
See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}.
+
{{empty section}}
 
 
==== Gen11 Graphics ====
 
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}.
 
  
== Die ==
+
==== Gen9.5 ====
=== Dual-core ===
+
See {{intel|Gen10#Gen10|l=arch}}.
* [[10 nm process]]
 
* [[13 metal layers]]
 
* ~8.2 mm x ~8.6 mm
 
* ~70.52 mm² die size
 
* 2 CPU cores + 40 GPU EUs
 
  
 
== All Cannon Lake Chips ==
 
== All Cannon Lake Chips ==
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           created and tagged accordingly.
 
           created and tagged accordingly.
  
           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
+
           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc6">
+
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
{{comp table header|main|7:List of Cannon Lake-based Processors}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannon Lake Chips</th></tr>
{{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
+
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 +
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannon Lake]] [[max cpu count::1]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?first launched
 
  |?release price
 
  |?release price
  |?first launched
+
  |?microprocessor family
 +
|?platform
 +
|?core name
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
 +
|?l3$ size
 +
|?l4$ size
 
  |?tdp
 
  |?tdp
 
  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|?integrated gpu max frequency
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|?has advanced vector extensions 2
 +
|?has intel trusted execution technology
 +
|?has transactional synchronization extensions
 +
|?has intel vpro technology
 +
|?has_intel_vt-d_technology
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
  |userparam=9
+
|searchlabel=
 +
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
  |userparam=25:19
 
  |mainlabel=-
 
  |mainlabel=-
 +
|limit=100
 
}}
 
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
+
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannon Lake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
  
 
== References ==
 
== References ==
* Some information was obtained directly from Intel.
 
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
  
 
== See also ==
 
== See also ==
 
* AMD's {{amd|Zen|l=arch}}
 
* AMD's {{amd|Zen|l=arch}}

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